is cleared to ?0?, rd strobe of pz0 is outputted (for pseudo sta tic ram) even when acces sing internal address. if remains ?1?, rd strobe signal is output only wh en external address area is accessed. figure 4-23 port z0 and z1 direction control (on bit basis) ? pzfc ytkvg pz ytkvg pz tgcf rd, wr 4gugv s a b s 1wvrwvncvej pz0 (rd) pz1 (wr) selector output buffer
page 86 2007-10-15 tmp91fw60 figure 4-24 port z2 and z3 function control (on bit basis) s 1wvrwvncvej pz2( hwr )  hwr   pzcr write pzfc write  pz write pz read s a b s pz3(r/ w )  r/ w   s a b p-ch (programmable pull up) p-ch (programmable pull up) output buffer output buffer pz read selector selector internal data bus internal data bus reset reset function control (on bit basis) direction control (on bit basis) direction control (on bit basis) pz write pzfc write pzcr write 1wvrwvncvej
page 87 2007-10-15 tmp91fw60 note 1: / is bit x of each register pzfc/pzcr. note 2: when port z is used as input mode, pz register controls internal pull-up resist or. read-modify-write instruction is proh ib- ited in input mode or i/o mode. setting the internal pull- up resistor may be depended on the states of the input pin. port z register 76543210 pz (007dh) bit symbol ? ? ? ? pz3 pz2 pz1 pz0 read/write ? ? ? ? r/w after reset ? ? ? ? data from external port (output latch register is set to ?1?.) 11 function ? 0 (output latch register): pull-up resistor off 1 (output latch register): pull-up resistor on output mode port z control register ( read-modify-write instructions are prohibited. ) 76543210 pzcr (007eh) bit symbol ? ? ? ? pz3c pz2c ? ? read/write ? ? ? ? w ? ? after reset????00?? function ? 0:input 1:output port z function register ( read-modify-write instructions are prohibited. ) 76543210 pzfc (007fh) bit symbol ? ? ? ? pz3f pz2f pz1f pz0f read/write ? ? ? ? w after reset????0000 function ? ? ? ? 0: port 1:r/ w 0: port 1: hwr 0: port 1: wr 0: port 1: rd pzxf pzxc pzx pz3 function pz2 function pz1 function pz0 function 0 0 0 input port input port output ?0?. output ?0?. 0 0 1 input port input port output ?1?. output ?1?. 0 1 0 output port output port output ?0?. output ?0?. 0 1 1 output port output port output ?1?. output ?1?. 100r/w reserved wr is output only during external accesses. always output rd .(corre- spond to pseudo sram) 101r/w reserved wr is output only during external accesses. rd is output only during external accesses. 1 1 0 reserved hwr wr is output only during external accesses. always output rd .(corre- spond to pseudo sram) 1 1 1 reserved hwr wr is output only during external accesses. rd is output only during external accesses.
page 88 2007-10-15 tmp91fw60 4.14 open-drain control p30,p31,p41,p90,p93,pb0,pb1 can perform selection of an open-drain output per bit. reset operation initializes all bits of the control register ode to ?0? and sets to cmos output. open-drain control register 76543210 ode (003fh) bit symbol ? odeb1 odeb0 ode93 ode90 ode41 ode31 ode30 read/write ? r/w after reset ? 0000000 function 0: cmos output 1:open drain output
page 89 2007-10-15 tmp91fw60 5. chip select/wait controller on the tmp91fw60, four user specifiab le address areas (cs0 to cs3) can be set. the data bus width and the number of waits can be set independently fo r each address area (cs0 to cs3 and others). the pins cs0 to cs3 (which can also function as port pins p40 to p43) are the respective output pins for the areas cs0 to cs3. when the cpu specifies an addr ess in one of these ar eas, the corresponding cs0 to cs3 pin outputs the chip select signal for the specified ad dress area (in rom or sram). however, in order for the chip select signal to be output, the port 6 function regi ster p4fc,p4fc2 must be set. the areas cs0 to cs3 are defined by the values in the memory start address registers msar0 to msar3 and the memory address mask registers mamr0 to mamr3. the chip select/wait control registers b0cs to b3cs and bexcs should be used to specify the master enable/dis- able status the data bus width and th e number of waits for each address area. the input pin controlling these states is the bus wait request pin ( wa i t ). 5.1 specifying an address area the cs0 to cs3 address areas are sp ecified using the start address regi sters (msar0 to msar3) and memory address mask register s (mamr0 to mamr3). at each bus cycle, a compare operation is performed to determine if the addr ess on the specified a location in the cs0 to cs3 area. if the result of the comparison is a matc h, this indicates an access to the corresponding cs area. in this case, the cs0 to cs3 pin outputs the chip select signal and the bus cycle operate s in accordance w ith the settings in chip select/wait control registers b0cs to b3cs. (see" 5.2 chip select/wait control registers ".) 5.1.1 memory start address registers the memory start address registers msar0 to msar3 set the start addre sses for the cs0 to cs3 areas. set the upper 8 bits (a23 to a16) of the start address in . the lower 16 bits of the start address (a15 to a0) are permanently set to 0. accordingly, the start address can only be set in 64-kbyte increments, starting from 000000h. figure 5-1 shows the relationship between the start addr ess and the start address register value. memory start address registers (for areas cs0 to cs3) 76543210 msar0 (00c8h) msar1 (00cah) msar2 (00cch) msar3 (00ceh) bit symbol s23 s22 s21 s20 s19 s18 s17 s16 read/write r/w after reset11111111 function determine a23 to a16 of start address (set start addresses for areas cs0 to cs3.)
page 90 2007-10-15 tmp91fw60 figure 5-1 relationship betw een start address and star t address register value 5.1.2 memory addr ess mask registers memory address mask registers ma mr0 to mamr3 are used to set th e size of the cs0 to cs3 areas by specifying a mask for each bit of the start address se t in memory start address registers mamr0 to mamr3. the compare operation used to determ ine if an address is in the cs0 to cs3 areas is only performed for bus address bits corresponding to bits set to ?0? in these registers. also, the address bits that can be masked by mamr0 to mamr3 differ between cs0 to cs3 areas. accordingly, the size that can be each area is different. note: range of possible settings for cs0 area size: 256 bytes to 2 mbytes. note: range of possible settings for cs1 area size: 256 bytes to 4 mbytes. note: range of possible settings for cs2 and cs3 area sizes: 32 kbytes to 8 mbytes. memory address mask register (for cs0 area) 76543210 mamr0 (00c9h) bit symbol v20 v19 v18 v17 v16 v15 v14 to v9 v8 read/write r/w after reset11111111 function set size of cs0 area 0: used for address compare memory address mask register (cs1) 76543210 mamr1 (00cbh) bit symbol v21 v20 v19 v18 v17 v16 v15 to v9 v8 read/write r/w after reset11111111 function set size of cs1 area 0: used for address compare memory address mask register (cs2, cs3) 76543210 mamr2 (00cdh) mamr3 (00cfh) bit symbol v22 v21 v20 v19 v18 v17 v16 v15 read/write r/w after reset11111111 function set size of cs1 area 0: used for address compare address 000000h ffffffh 000000h 010000h 020000h 030000h 040000h 050000h 060000h to ff0000h 00h 01h 02h 03h 04h 05h 06h to ffh start address value in start address register (msar0 to msar3) 64 kbytes
page 91 2007-10-15 tmp91fw60 5.1.3 setting memory star t addresses and address areas figure 5-2 shows an example of specifying a 64-kbyte addr ess area starting from 010000h using the cs0 areas. set ?01h? in memory start address register msar0 (corresponding to the upper 8 bits of the start address). next, calculate the difference between the st art address and the anticipat ed end address (01ffffh). bits 20 to 8 of the result correspond to the mask value to be set for the cs0 area. setting this value in memory address mask register mamr0 sets the area size. this example sets ?07h? in ma mr0 to specify a 64-kbyte area. figure 5-2 example showi ng how to set the cs0 area after a reset, msar0 to msar3 and mamr0 to ma mr3 are set to ?ffh?. b0cs, b1cs and b3cs are reset to ?0?. this disables the cs 0, cs1 and cs3 areas. however, as b2cs to ?0? and b2cs to ?1?, cs2 is enabled ?002000 to fdffff? in tmp91fw60. also, the bus width and num- ber of waits specified in bexcs are used for accessi ng addresses outside the specified cs0 to cs3 area. 1 tu]&3
l <_, tu]<_, q,"_+,2 .3oo tu] ,2o; <_, cs0 $4f (- (64 k c; ) "07h"  .3o???a 64 k c;$4f 0oa?? 00000001 0000000111111111 s23 s22 s21 s20 s19 s18 s17 s16 v20 v19 v18 v17 v16 v15 v14 ~ v9 v8 01ffff 01h 11111111 07h msar0 00000000 1 1 1 111111111111 msmr0 h
page 92 2007-10-15 tmp91fw60 5.1.4 address area si ze specification table 5-1 shows the relationship between cs area and area size. ? ? indicates areas that cannot be set by memory start address register and a ddress mask register combinations. wh en setting an area size using a com- bination indicated by ? ?, set the start address mask register in the desired steps starting from 000000h. if the cs2 area is set to 16 mbytes or if two or mo re areas overlap, the smaller cs area number has the higher priority. 5.1.4.1 to set the area size for cs0 to 128 kbytes: note: ? ? indicates areas that cannot be set by memory start address register and address mask register combinations. example: valid start addresses 000000h any of these addresses may be set as the start address. (128 kbytes) 020000h (128 kbytes) 040000h (128 kbytes) 060000h : example: invalid start addresses 000000h this is not an integer multiple of the desired area size setting. hence, none of these addresses can be set as the start address. (64 kbytes) 010000h (128 kbytes) 030000h (128 kbytes) 050000h : table 5-1 valid area sizes for each cs area size (bytes) 256 512 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m cs area cs0 ???????? cs1 ? ?????? cs2 ???????? cs3 ????????
page 93 2007-10-15 tmp91fw60 5.2 chip select/wait control registers the master enable/disable, chip se lect output waveform, data bus wi dth and number of wait states for each address area (cs0 to cs3 and others) are set in their respec tive chip select/wait control re gisters, b0cs to b3cs and bexcs. chip select/wait control registers 76543210 b0cs (00c0h) rmw instructions are prohib- ited. bit symbol b0e - b0om1 b0om0 b0bus b0w2 b0w1 b0w0 read/write w - w after reset0 - 000000 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait b1cs (00c1h) rmw instructions are prohib- ited. bit symbol b1e - b1om1 b1om0 b1bus b1w2 b1w1 b1w0 read/write w - w after reset0 - 000000 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait b2cs (00c2h) rmw instructions are prohib- ited. bit symbol b2e b2m b2om1 b2om0 b2bus b2w2 b2w1 b2w0 read/write w w after reset10000000 function 0: disable 1: enable cs2 area selection 0: 16-mbyte area 1: cs area chip select output waveform selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait b3cs (00c3h) rmw instructions are prohib- ited. bit symbol b3e - b3om1 b3om0 b3bus b3w2 b3w1 b3w0 read/write w - w after reset0 - 000000 function 0: disable 1: enable chip select output waveform selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait master enable bit cs2 area selection bne (n = 0 to 3) 0 disable b2m 0 16-mbyte area 1 enable 1 specified address area chip select output waveform selection data bus width selection bnom1:0 (n = 0 to 3) 00 for rom/sram bnbus (n = 0 to ex) 0 16-bit data bus 01 don?t care 1 8-bit data bus 10 11
page 94 2007-10-15 tmp91fw60 5.2.1 master enable bits bit7 (, , or ) of a chip select /wait control register is the master bit which is used to enable or disable settings for the corresponding addres s area. writing ?1? to this bit enables the settings. reset disables (sets to ?0?) , and , and enabled (sets to ?1?) . this enables area cs2 only. 5.2.2 data bus width selection bit3 (, , , or ) of a chip sel ect/wait control register specifies the width of the data bus. this bit should be set to ?0? when memory is to be accessed using a 16-bit data bus and to ?1? when an 8-bit data bus is to be used. this process of changing the data bus width accord ing to the address being accessed is known as ?dynamic bus sizing?. for details of this bus operation see table 5-2. 76543210 bexcs (00c7h) rmw instructions are prohib- ited. bit symbol ? ? ? ? bexbus bexw2 bexw1 bexw0 read/write ? ? ? ? w after reset????0000 function data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait number of address area waits bnw2:0 (n = 0 to ex) see" 5.2.3 wait control "
page 95 2007-10-15 tmp91fw60 note:?xxxxx? indicates that the input dat a from these bits are ignored during a read. during a write, indicates that the bus for these bits goes too high impedance; also, t hat the write strobe signal for the bus remains inactive. 5.2.3 wait control bits 0 to 2 (, , , , ) of a chip select/wait control reg- ister specify the number of waits that are to be in serted when the correspondi ng memory area is accessed. the following types of wait operation can be specified using these bits. bit settings other than those listed in the table should not be made. a reset sets these bit to ? 000 ? (2 waits). table 5-2 dynamic bus sizing operand data bus width operand start address memory data bus width cpu address cpu data d15 to d8 d7 to d0 8 bits 2n + 0 (even number) 8 bits 2n + 0 xxxxx b7 to b0 16 bits 2n + 0 xxxxx b7 to b0 2n + 1 (odd number) 8 bits 2n + 1 xxxxx b7 to b0 16 bits 2n + 1 b7 to b0 xxxxx 16 bits 2n + 0 (even number) 8 bits 2n + 0 2n + 1 xxxxx xxxxx b7 to b0 b15 to b8 16 bits 2n + 0 b15 to b8 b7 to b0 2n + 1 (odd number) 8 bits 2n + 1 2n + 2 xxxxx xxxxx b7 to b0 b15 to b8 16 bits 2n + 1 2n + 2 b7 to b0 xxxxx xxxxx b15 to b8 32 bits 2n + 0 (even number) 8 bits 2n + 0 2n + 1 2n + 2 2n + 3 xxxxx xxxxx xxxxx xxxxx b7 to b0 b15 to b8 b23 to b16 b31 to b24 16 bits 2n + 0 2n + 2 b15 to b8 b31 to b24 b7 to b0 b23 to b16 2n + 1 (odd number) 8 bits 2n + 1 2n + 2 2n + 3 2n + 4 xxxxx xxxxx xxxxx xxxxx b7 to b0 b15 to b8 b23 to b16 b31 to b24 16 bits 2n + 1 2n + 2 2n + 4 b7 to b0 b23 to b16 xxxxx xxxxx b15 to b8 b31 to b24 table 5-3 wait operation settings number of waits wait operation 000 2 waits inserts a wait of 2 states, irrespective of the wait pin state. 001 1 wait inserts a wait of 1 state, irrespective of the wait pin state. 010 (1 + n) waits samples the state of the wait pin after inserting a wait of one state. if the wait pin is low, the waits continue and the bus cycle is extended until the pin goes high. 011 0 waits ends the bus cycle without a wait, regardless of the wait pin state. 100 reserved invalid setting 101 3 waits inserts a wait of 3 state, irrespective of the wait pin state. 110 4 waits inserts a wait of 4 state, irrespective of the wait pin state. 111 8 waits inserts a wait of 8 state, irrespective of the wait pin state.
page 96 2007-10-15 tmp91fw60 5.2.4 bus width and wait control for an area other than cs0 to cs3 the chip select/wait control register bexcs controls the bus width and number of waits when memory loca- tions which are not in one of the four user-specified address areas (cs0 to cs3) are accessed. the bexcs reg- ister settings are always enabled for areas other than cs0 to cs3. 5.2.5 selecting 16-mbyte area/specified address area setting b2cs (bit6 of the chip select/wait cont rol register for cs2) to ?0? designates the 16-mbyte area ?002000 to fdffff? as the cs2 area. setting b2cs to ?1? designates the address area specified by the start address register msar2 and the address mask register mamr2 as cs2 (e.g., if b2cs = 1, cs2 is specified in the same ma nner as cs0, cs1 and cs3 are). a reset clears this bit to ?0?, speci fying cs2 as a 16-mbyte address area. 5.2.6 procedure for settin g chip select/wait control when using the chip select/wai t control function, set the registers in the following order: 1. set the memory start addres s registers msar0 to msar3. set the start addresses for cs0 to cs3. 2. set the memory address mask registers mamr0 to mamr3. set the sizes of cs0 to cs3. 3. set the chip select/wait cont rol registers b0cs to b3cs. set the chip select output waveform, data bus width, number of waits and master enable/disable status for cs0 to cs3 . the cs0 to cs3 pins can also function as pins p40 to p 43. to output a chip select signal using one of these pins, set the corresponding bit in the port 6 function register p4fc/p4fc2 to ?1?. if a cs0 to cs3 address is specifi ed which is actually an internal i/o and ram area address, the cpu accesses the internal address area and no chip select signal is output on any of the cs0 to cs3 pins. example :in this example cs0 is set to the 64-kbyte area 010000h to 01ffffh. the bus width is set to 16 bits and the number of waits is set to 0. ld (msar0), 01h ; start address: 010000h ld (mamr0), 07h ; address area: 64 kbytes ld (b0cs), 83h ; rom/sram, 16-bit data bus, 0 waits, cs0 area settings enabled
page 97 2007-10-15 tmp91fw60 5.3 connecting external memory figure 5-3 shows an example of how to connect external memory to tmp91fw60. in this example the rom is connected using a 16-bit bus. the ram and i/o are connected using an 8-bit bus. figure 5-3 example of ex ternal memory connection (rom uses 16-bit bus, ra m and i/o use 8-bit bus. a reset clears all bits of the port 4 control register p4cr and the port 4 fu nction register p4fc/p4fc2 to ?0? and disables output of the cs signal. to output the cs signal, the appropriate bit must be set to ?1?. oe wr we rd ale ad0~ad7 ad8~ad15 address bus cs2 cs1 cs0 cs upper byte rom oe cs lower byte rom we oe cs 8-bit bus ram oe cs 8-bit bus i/o d le q d le q 74ac573 tmp91fw60
page 98 2007-10-15 tmp91fw60 6. 8-bit timers (tmra) the tmp91fw60 features 6 channels (tmr a0 to tmra5) built-in 8-bit timers. these timers are paired into 3 mo dules: tmra01, tmra23 and tmra45. each module consists of 2 channels and can operate in any of the following 4 operating modes. ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable square wave pulse generation output mode (ppg ? variable duty cycle with variable period) ? 8-bit pulse width modulation output mode (pwm ? variable duty cycle with constant period) figure 6-1 to figure 6-3 show block diagrams for tmra01, tmra23 and tmra45. each channel consists of an 8-bit up counter, an 8-bit comp arator and an 8-bit timer register. in addition, a timer flip-flop and a prescaler are prov ided for each pair of channels. the operation mode and timer flip-flops are controlled by 5-byte registers sfrs (special function registers). each of the three modules (tmra01, tmra23 and tmra45) can be operated independently. all modules oper- ate in the same manner; hence only the operation of tmra01 is explained here. table 6-1 registers and pins for each module specification module tmra01 tmra23 tmra45 external pin input pin for external clock ta0in (shared with p70) none ta4in (shared with p73) output pin for timer flip-flop ta1out (shared with p71) ta3out (shared with p72) ta5out (shared with p74) sfr (address) timer run register ta01run (0100h) ta23run (0108h) ta45run (0110h) timer register ta0reg (0102h) ta1reg (0103h) ta2reg (010ah) ta3reg (010bh) ta4reg (0112h) ta5reg (0113h) timer mode register ta01mod (0104h) ta23mod (010ch) ta45mod (0114h) timer flip-flop control register ta1ffcr (0105h) ta3ffcr (010dh) ta5ffcr (0115h)
page 99 2007-10-15 tmp91fw60 6.1 block diagrams figure 6-1 tmra01 block diagram 8-bit up counter (uc0) timer  flip-flop ta1ff 8-bit comparator (cp0) 2 4 8 16 32 64 128 256 512 8-bit timer register ta0reg register buffer 0 t1 t1 prescaler clock: t0 external input clock: ta0in timer flip-flop output: ta1out tmra0 interrupt output: intta0 tmra1 interrupt output: intta1 tmra0 match output: ta0trg prescaler t4 t4 t16 t16 ta01mod ta1ffcr ta01mod ta01run ta01mod ta01mod ta0trg ta01run ta01run t256 ta01run run/clear 2 n overflow 8-bit comparator (cp1) 8-bit up counter (uc1) 8-bit timer register ta1reg match detect match detect selector t1 t16 t256 selector internal data bus internal data bus
page 100 2007-10-15 tmp91fw60 figure 6-2 tmra23 block diagram 8-bit up counter (uc2) timer flip-flop ta3ff 8-bit comparator (cp2) 2 4 8 16 32 64 128 256 512 8-bit timer register ta2reg register buffer 2 t1 t1 prescaler clock: t0 timer flip-flop output: ta3out tmra2 interrupt output: intta2 tmra3 interrupt output: intta3 tmra2 match output: ta2trg prescaler t4 t4 t16 t16 ta23mod ta3ffcr ta23mod ta23run ta23mod ta23mod ta2trg ta23run ta23run t256 ta23run run/clear 2 n overflow 8-bit comparator (cp3) 8-bit up counter (uc3) 8-bit timer register ta3reg match detect match detect selector t1 t16 t256 selector internal data bus internal data bus
page 101 2007-10-15 tmp91fw60 figure 6-3 tmra45 block diagram 8-bit up counter (uc4) timer  flip-flop ta5ff 8-bit comparator (cp4) 2 4 8 16 32 64 128 256 512 8-bit timer register ta4reg register buffer 4 t1 t1 prescaler clock: t0 external input clock: ta4in timer flip-flop output: ta5out tmra4 interrupt output: intta4 tmra5 interrupt output: intta5 tmra4 match output: ta4trg prescaler t4 t4 t16 t16 ta45mod ta5ffcr ta45mod ta45run ta45mod ta45mod ta4trg ta45run ta45run t256 ta45run run/clear 2 n overflow 8-bit comparator (cp5) 8-bit up counter (uc5) 8-bit timer register ta5reg match detect match detect selector t1 t16 t256 selector internal data bus internal data bus
page 102 2007-10-15 tmp91fw60 6.2 operation of each circuit 6.2.1 prescalers a 9-bit prescaler generates the input clock to tmra01. the ? t0? as the input clock to prescaler is a clock divided by 4 which is selected using the prescaler clock selection register syscr0. the prescaler?s operation can be controlled using ta01run in the timer control register. set- ting to ?1? starts the count; setting to ?0? clears the prescaler to ?0? and stops operation. table 6-2 shows the various prescaler output clock resolutions. note: xxx: don?t care 6.2.2 up counters (uc0 and uc1) these are 8-bit binary counters which count up the input clock pulses for the clock specified by ta01mod. the input clock for uc0 is selectable and can be either the external clock input via the ta0in pin or one of the three internal clocks t1, t4, or t16. the clock setting is specified by the value set in ta01mod. the input clock for uc1 depends on the operation mode. in 16-bit timer mode, the overflow output from uc0 is used as the input clock. in any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks t1, t16 or t256, or the comparator output (the match detection signal) from tmra0. for each interval timer the timer operation control register bits ta01run and ta01run can be used to stop and clear the up counters and to control th eir count. a reset clears both up counters, stopping the timers. table 6-2 prescaler output clock resolution @ fc = 20 mhz, fs = 32.768 khz system clock selection syscr1 gear value syscr1 prescaler clock selection syscr0 prescaler output clock resolution t1 (1/2) t4 (1/8) t16 (1/32) t256 (1/512) 1 (fs) xxx 0 (1/1) f fph 2 3 /fs (244 s) 2 5 /fs (977 s) 2 7 /fs (3.9 ms) 2 11 /fs (62.5 ms) 0 (fc) 000 (fc) 2 3 /fc (0.4 s) 2 5 /fc (1.6 s) 2 7 /fc(6.4 s) 2 11 /fc (102.4 s) 001 (fc/2) 2 4 /fc (0.8 s) 2 6 /fc (3.2 s) 2 8 /fc (12.8 s) 2 12 /fc (204.8 s) 010 (fc/4) 2 5 /fc (1.6 s) 2 7 /fc (6.4 s) 2 9 /fc (25.6 s) 2 13 /fc (409.6 s) 011 (fc/8) 2 6 /fc (3.2 s) 2 8 /fc (12.8 s) 2 10 /fc (51.2 s) 2 14 /fc (819.2 s) 100 (fc/16) 2 7 /fc (6.4 s) 2 9 /fc (25.6 s) 2 11 /fc (102.4 s) 2 15 /fc (1638.4 s) xxx 1 (1/16) fc/16 clock 2 7 /fc (6.4 s) 2 9 /fc (25.6 s) 2 11 /fc (102.4 s) 2 15 /fc (1638.4 s)
page 103 2007-10-15 tmp91fw60 6.2.3 timer register s (ta0reg and ta1reg) these are 8-bit registers which can be used to set a ti me interval. when the value set in the timer register ta0reg or ta1reg matches the value in the correspond ing up counter, the compar ator match detect signal goes active. if the value set in the timer register is 00 h, the signal goes active when the up counter overflows. the ta0reg are double buffer structure, each of which makes a pair with register buffer. the setting of the bit ta01run determines whether ta0reg?s double buffer structure is enabled or disabled. it is di sabled if = ?0? a nd enabled if = ?1?. when the double buffer is enabled, data is transferred fr om the register buffer to the timer register when a 2 n overflow occurs in pwm mode, or at the start of the ppg cycle in ppg mode. hence the double buffer cannot be used in timer mode. a reset initializes to ?0?, disabling the double buffer. to use the double buffer, write data to the timer register, set to ?1?, and write the follow ing data to the register buffer. figure 6-4 shows the configuration of ta0reg. figure 6-4 configuration of ta0reg note:the same memory address is allocated to the timer register ta0reg and the register buffer 0. when = 0, the same value is written to the r egister buffer 0 and the timer register ta0reg; when = 1, only the register buffer 0 is written to. write selector shift trigger matching detection in ppg cycle 2 n overflow pwm timer registers 0 (ta0reg) register buffers 0 internal data bus s y a b write to ta0reg ta01run
page 104 2007-10-15 tmp91fw60 6.2.4 comparator (cp0 and cp1) the comparator compares the value in an up counter with the value set in a timer register. if they match, the up counter is cleared to 0 and an interrupt signal (intta0 or intta1) is generated. if timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. note:if a value smaller than the up-counter value is written to the timer register while the timer is counting up, this will cause the timer to overflow and an interrupt cannot be generated at the expected time. (the value in the timer register can be changed without any problem if the new value is larger than the up-counter value.) in 16- bit interval timer mode, be sure to write to both ta0reg and ta1reg in this order (16 bits in total), the com- pare circuit will not function if only the lower 8 bits are set. 6.2.5 timer flip-flop (ta1ff) the timer flip-flop (ta1ff) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. whether inversion is enabled or disabled is determined by the setting of the bit ta1ffcr in the timer flip-flop control register. a reset clears the value of ta1ff1 to ?0?. writing ?01? or ?10? to ta1ffcr sets ta1 ff to 0 or 1. writing ?00? to these bits inverts the value of ta1ff (this is known as software inversion). the ta1ff signal is output via the ta1out pin (concurrent with p71). when this pin is used as the timer output, the timer flip-flop should be set beforehand using the port 7 function registers p7cr, p7fc. note: if an inversion by the match-detect signal and a setting c hange via the tmra1 flip-flop cont rol register occur simulta- neously, the resultant operation varies depending on the situation, as shown below. ? if an inversion by the match-detect signal and an inversion via the register occu r simultaneously, the flip-flop will be inverted only once. ? if an inversion by the match-detect signal and an atte mpt to set the flip-flop to 1 via the register occur simultaneously, the timer flip-flop will be set to 1. ? if an inversion by the match-detect signal and an atte mpt to clear the flip-flop to 0 via the register occur simultaneously the flip-flop will be cleared to 1. be sure to stop the timer before changing the flip-flop insertion setting. if the setting is changed while the timer is counting, proper operation cannot be obtained. the condition for ta1ff inversion varies with mode as shown below 8-bit interval timer mode : uc0 matches ta0reg or uc1 matches ta1reg (select either one of the two) 16-bit interval timer mode : uc0 matches ta0reg or uc1 matches ta1reg 8 bit pwm mode : uc0 matches ta0reg or a 2n overflow occurs 8 bit ppg mode : uc0 matches ta0reg or uc0 matches ta1reg
page 105 2007-10-15 tmp91fw60 6.3 sfr note: the values of bits 4 to 6 of ta01run are "1" when read. note: the values of bits 4 to 6 of ta23run are "1" when read. note: the values of bits 4 to 6 of ta45run are "1" when read. tmra01 run register 76543210 ta01run (0100h) bit symbol ta0rde ? ? ? i2ta01 ta01prun ta1run ta0run read/write r/w ? ? ? r/w after reset0???0000 function double buffer 0: disable 1: enable idle2 0: stop 1: operate tmra01 prescaler up counter (uc1) up counter (uc0) 0: stop and clear 1: run (count up) count operation ta0reg double buffer control ta01prun ta1run / ta0run 0 stop and clear ta0rde 0 disable 1 run (count up) 1 enable tmra23 run register 76543210 ta23run (0108h) bit symbol ta2rde ? ? ? i2ta23 ta23prun ta3run ta2run read/write r/w ? ? ? r/w after reset0???0000 function double buffer 0: disable 1: enable idle2 0: stop 1: operate tmra23 prescaler up counter (uc3) up counter (uc2) 0: stop and clear 1: run (count up) count operation ta2reg double buffer control ta23prun ta3run / ta2run 0 stop and clear ta2rde 0 disable 1 run (count up) 1 enable tmra45 run register 76543210 ta45run (0110h) bit symbol ta4rde ? ? ? i2ta45 ta45prun ta5run ta4run read/write r/w ? ? ? r/w after reset0???0000 function double buffer 0: disable 1: enable idle2 0: stop 1: operate tmra45 prescaler up counter (uc5) up counter (uc4) 0: stop and clear 1: run (count up) count operation ta4reg double buffer control ta45prun ta5run / ta4run 0 stop and clear ta4rde 0 disable 1 run (count up) 1 enable
page 106 2007-10-15 tmp91fw60 tmra01 mode register 76543210 ta01mod (0104h) bit symbol ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 read/write r/w after reset00000000 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 input clock for tmra1 00: ta0trg 01: t1 10: t16 11: t256 input clock for tmra0 00: ta0in pin 01: t1 10: t4 11: t16 tmra0 input clock selection 00 ta0in?? 01 t1 10 t4 11 t16 tmra1 input clock selection ta01mod 01 ta01mod = 01 00 comparator output from tmra0 overflow output from tmra0 (16-bit timer mode) 01 t1 10 t16 11 t256 pwm cycle selection 00 reserved 01 2 6 clock source 10 2 7 clock source 11 2 8 clock source tmra01 operation mode selection 00 8-bit timers 2ch 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra0) + 8-bit timer (tmra1)
page 107 2007-10-15 tmp91fw60 tmra23 mode register 76543210 ta23mod (010ch) bit symbol ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 read/write r/w after reset00000000 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 input clock for tmra3 00: ta2trg 01: t1 10: t16 11: t256 input clock for tmra2 00: reserved 01: t1 10: t4 11: t16 tmra2 input clock selection 00 reserved 01 t1 10 t4 11 t16 tmra3 input clock selection ta23mod 01 ta23mod = 01 00 comparator output from tmra2 overflow output from tmra2 (16-bit timer mode) 01 t1 10 t16 11 t256 pwm cycle selection 00 reserved 01 2 6 clock source 10 2 7 clock source 11 2 8 clock source tmra23 operation mode selection 00 8-bit timers 2ch 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra2) + 8-bit timer (tmra3)
page 108 2007-10-15 tmp91fw60 tmra45 mode register 76543210 ta45mod (0114h) bit symbol ta45m1 ta45m0 pwm41 pwm40 ta5clk1 ta5clk0 ta4clk1 ta4clk0 read/write r/w after reset00000000 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 input clock for tmra5 00: ta4trg 01: t1 10: t16 11: t256 input clock for tmra4 00: ta4in pin 01: t1 10: t4 11: t16 tmra4 input clock selection 00 ta4in 01 t1 10 t4 11 t16 tmra5 input clock selection ta45mod 01 ta45mod = 01 00 comparator output from tmra4 overflow output from tmra4 (16-bit timer mode) 01 t1 10 t16 11 t256 pwm cycle selection 00 reserved 01 2 6 clock source 10 2 7 clock source 11 2 8 clock source tmra45 operation mode selection 00 8-bit timers 2ch 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra4) + 8-bit timer (tmra5)
page 109 2007-10-15 tmp91fw60 note: the values of bits 4 to 7 of ta1ffcr are "1" when read. note: the values of bits 4 to 7 of ta3ffcr are "1" when read. tmra1 flip-flop control register 76543210 ta1ffcr (0105h) bit symbol ? ? ? ? ta1ffc1 ta1ffc0 ta1ffie ta1ffis read/write ? ? ? ? r/w r/w after reset????1100 function 00: invert ta1ff 01: set ta1ff 10: clear ta1ff 11: don?t care ta1ff control for inversion 0: disable 1: enable ta1ff inversion select 0: tmra0 1:tmra1 inverse signal for timer flip-flop 1 (ta1ff ) (don?t care except in 8-bit timer mode) ta1ffis 0 inversion by tmra0 1 inversion by tmra1 inversion of ta1ff ta1ffie 0 disabled 1 enabled control of ta1ff 00 inverts the value of ta1ff (software inversion) 01 sets ta1ff to ?1? 10 clears ta1ff to ?0? 11 don?t care tmra3 flip-flop control register 76543210 ta3ffcr (010dh) bit symbol ? ? ? ? ta3ffc1 ta3ffc0 ta3ffie ta3ffis read/write ? ? ? ? r/w r/w after reset????1100 function 00: invert ta3ff 01: set ta3ff 10: clear ta3ff 11: don?t care ta3ff control for inversion 0: disable 1: enable ta3ff inversion select 0: tmra2 1:tmra3 inverse signal for timer flip-flop 3 (ta3ff ) (don?t care except in 8-bit timer mode) ta3ffis 0 inversion by tmra2 1 inversion by tmra3 inversion of ta3ff ta3ffie 0 disabled 1 enabled control of ta3ff 00 inverts the value of ta3ff (software inversion) 01 sets ta3ff to ?1? 10 clears ta3ff to ?0? 11 don?t care
page 110 2007-10-15 tmp91fw60 note: the values of bits 4 to 7 of ta5ffcr are "1" when read. tmra5 flip-flop control register 76543210 ta5ffcr (0115h) bit symbol ? ? ? ? ta5ffc1 ta5ffc0 ta5ffie ta5ffis read/write ? ? ? ? r/w r/w after reset????1100 function 00: invert ta5ff 01: set ta5ff 10: clear ta5ff 11: don?t care ta5ff control for inversion 0: disable 1: enable ta5ff inversion select 0: tmra4 1:tmra5 inverse signal for timer flip-flop 5 (ta5ff ) (don?t care except in 8-bit timer mode) ta5ffis 0 inversion by tmra4 1 inversion by tmra5 inversion of ta5ff ta5ffie 0 disabled 1 enabled control of ta5ff 00 inverts the value of ta5ff (software inversion) 01 sets ta5ff to ?1? 10 clears ta5ff to ?0? 11 don?t care timer register 76543210 ta0reg (0102h) bit symbol ? read/write w after reset 0 ta1reg (0103h) bit symbol ? read/write w after reset 0 ta2reg (010ah) bit symbol ? read/write w after reset 0 ta3reg (010bh) bit symbol ? read/write w after reset 0 ta4reg (0112h) bit symbol ? read/write w after reset 0 ta5reg (0113h) bit symbol ? read/write w after reset 0
page 111 2007-10-15 tmp91fw60 6.4 operation in each mode 6.4.1 8-bit timer mode both tmra0 and tmra1 can be used independently as 8-bit interval timers. set its function or counter data for tmra0 and tmra1 after stop these registers. 6.4.1.1 generating interrupts at a fixed interval (using tmra1) to generate interrupts at constant intervals using tmra1 (intta1), first stop tmra1 then set the operation mode, input clock and a cycle to ta01mod and ta1reg regi ster, respectively. then, enable the interrupt intta1 and start tmra1 counting. note: x: don?t care, ?: no change select the input clock using table 6-2. note: the input clocks for tmra0 and tm ra1 are different from as follows. tmra0: ta0in input, t1, t4 or t16 tmra1: match output of tmra0, t1, t16, t256 example: to generate an intta1 interrupt every 12 s at fc = 20 mhz, set e ach register as follows: * clock state system clock : high frequency (fc) prescaler clock : f fph clock gear : 1 (fc) msb lsb 76543210 ta01run ?xxx??0?stop tmra1 and clear it to 0. ta01mod 00xx01xx select 8-bit timer mode and select t1 (0.4 s at fc = 20 mhz) as the input clock. ta1reg 00011110set ta1reg to 12 s t1 = 30 = 1eh inteta01 x 1 0 1 x ? ? ? enable intta1 and set it to level 5. ta01run ?xxx?11?start tmra1 c ounting.
page 112 2007-10-15 tmp91fw60 6.4.1.2 generating a 50% duty ratio square wave pulse the state of the timer flip-flop (ta1 ff) is inverted at constant intervals and its status output via the timer output pin (ta1out). note: x: don?t care, ?: no change example: to output a 2.4 s square wave pulse from the ta1out pin at fc = 20 mhz, use the following procedure to make the appropriate register settings . this example uses tmra1; however, either tmra0 or tmra1 may be used. * clock state system clock : high frequency (fc) prescaler clock : f fph clock gear : 1 (fc) msb lsb 76543210 ta01run ?xxx??0?stop tmra1 and clear it to 0. ta01mod 00xx01?? select 8-bit timer mode and select t1 (0.4 s at fc = 20 mhz) as the input clock. ta1reg 00000011set the timer register to 2.4 s t1 2 = 03h ta1ffcr xxxx 1011 clear ta1ff to ?0? and set it to invert on the match detects signal from tmra1. p7cr xxx???1? set p71 to function as the ta1out pin. p7fc xxx???1? ta01run ?xxx?11?start tmra1 counting.
page 113 2007-10-15 tmp91fw60 figure 6-5 square wave ou tput timing chart (50% duty) 6.4.1.3 making tmra1 count up on the match signal from the tmra0 comparator select 8-bit timer mode and set the comparator output from tmra0 to be the input clock to tmra1. figure 6-6 tmra 1 count up on si gnal from tmra0 intta1 ta1ff ta1out bit1 uc1 clear up counter comparator timig comparator output (match detect) bits 7 to 2 ta01run
t t1 bit0 0.9
? s at fc = 20 mhz 333 222 111 0000 2 1 345123 23 451 1 2 1 tmra0 up counter (when ta0reg = 5) tmra1 up counter (when ta1reg = 2) comparator output (tmra0 match) tmra1 match output
page 114 2007-10-15 tmp91fw60 6.4.2 16-bit timer mode a 16-bit interval timer is configured by pairing the two 8-bit timers tmra0 and tmra1. to make a 16-bit interval timer in which tmra0 and tmra1 are cascaded together, set ta01mod to 01. in 16-bit timer mode, the overflow output from tmra0 is used as the input clock for tmra1, regardless of the value set in ta01mod. table 6-2 shows the cycle of the input clock for tmra0. lsb 8-bit set to ta0reg and msb 8- bit is for ta1reg. please keep se tting ta0reg first because setting data for ta0reg inhibit its compare function and setting data for ta1reg permit it. if t16 (2 7 /fc s at fc = 20 mhz) is used as the input clock fo r counting, set the following value in the regis- ters: 0.4 s/(2 7 /fc) s P 62500 = f424h (e.g., set ta1reg to f4h and ta0reg to 24h). as a result, intta1 interrupt can be generated every 0.4 [s]. the comparator match signal is output from tm ra0 each time the up counter uc0 matches ta0reg, though the up counter uc0 is not cleared and also intta0 is not generated. in the case of the tmra1 comparator, the match det ect signal is output on each comparator pulse on which the values in the up counter uc1 and ta1reg match. when the match detect signal is ou tput simultaneously from both th e comparators tmra0 and tmra1, the up counters uc0 and uc1 are cleared to 0 and the interrupt intta1 is generated. also, if inversion is enabled, the value of the timer flip-flop ta1ff is inverted. example: when ta1reg = 04h and ta0reg = 80h figure 6-7 timer output by 16-bit timer mode example: to generate an intta1 interrupt every 0.4 [s] at fc = 20 mhz, set the timer registers ta0reg and ta1reg as follows: * clock state system clock : high frequency (fc) prescaler clock : f fph clock gear : 1 (fc) inversion interrupt intta1 timer output ta1out 0080h 0180h 0280h 0380h 0480h 0080h tmra0 comparator match detect signal value of up counter (uc1, uc0) tmra1 comparator match detect signal interrupt intta0
page 115 2007-10-15 tmp91fw60 6.4.3 8-bit ppg (programmabl e pulse generation) output mode square wave pulses can be generated at any frequency and duty ratio by tmra0. the output pulses may be active low or active high. in this mode tmra1 cannot be used. tmra0 outputs pulses on the ta1out pin. figure 6-8 8-bit ppg output waveforms in this mode, a programmable square wave is genera ted by inverting the timer output each time the 8-bit up counter (uc0) matches the value in one of the timer registers ta0reg or ta1reg. the value set in ta0reg must be smaller than the value set in ta1reg. although the up counter for tmra1 (uc1) is not used in this mode, ta01run should be set to ?1?, so that uc1 is set for counting. figure 6-9 shows a block diagram representing this mode. figure 6-9 block diagram of 8-bit ppg output mode ta1out ta1reg t h t t l ta0reg ta0reg and uc0 match (interrupt intta0) ta1reg and uc0 match (interrupt intta1) t l t t h = "10" = "01" example: = "01" selector selector shift trigger comparator register buffer comparator ta1reg internal data bus ta01run ta0reg-wr 8-bit up counter (uc0) ta1ff ta1out intta0 intta1 ta1ffcr ta01mod ta01run inversion ta0in t1 t4 t16 ta0reg
page 116 2007-10-15 tmp91fw60 if the ta0reg double buffer is enabled in this mode, the value of the register buffer will be shifted into ta0reg each time ta1reg matches uc0. use of the double buffer facilitates the handlin g of low-duty waves (when duty is varied). figure 6-10 operation of register buffer 0 note:the values that can be set in taxreg range from 01h to 00h (equivalent to 100h). if the maximum value 00h is set, the match-detect signal goes ac tive when the up-counter overfolws. example: to generate 1/4-duty 50-khz pulses (at fc = 20 mhz): calculate the value which should be set in the timer register. to obtain a frequency of 50 khz, the pulse cycle t should be: t = 1/50 khz = 20 s t1 = 2 3 /fc s (at fc = 20 mhz); 20 s/(2 3 /fc) s = 50 therefore set ta1reg to 50 (32h), and 50-khz pulses can be obtained. the duty is to be set to 1/4: t 1/4 = 20 s 1/4 = 5 s 5 s/(2 3 /fc) s P 13 therefore, set ta0reg = 13 = 0dh. * clock state system clock : high frequency (fc) prescaler clock : f fph clock gear : 1 (fc) q 2 q 1 match wiht ta1reg ta0reg (value to be compared) q 3 q 2 register buffer shift from register buffer 0 ta0reg (register buffer 0) write (up counter = q 1 ) (up counter = q 2 ) match with ta0reg and up counter 20
? s
page 117 2007-10-15 tmp91fw60 note:x : don't care ? : no change 76543210 ta01run 0xxx??00 stop tmra0 and tmra01 and clear it to ?0?.(double buffer dis- able) ta01mod 1 0xxxx0 1set the 8-bit ppg m ode, and select t1 as input clock. ta0reg 00001101write 0dh. ta1reg 00110010write 32h. ta1ffcr xxxx0 1 1xset ta1ff, enabling both inversion and the double buffer. writing ?10? provides negative logic pulse. p7cr xxx???1? set p71 as the ta1out pin. p7fc xxx???1? ta01run 1xxx?111start tmra0 and tmra01 counting.(double buffer enable)
page 118 2007-10-15 tmp91fw60 6.4.4 8-bit pwm output mode this mode is only valid for tmra0. in this mode, a pwm pulse with the maximum resolution of 8 bits can be output. when tmra0 is used the pwm pulse is output on the ta1out pin. tmra1 can also be used as an 8-bit timer. the timer output is inverted when the up counter (uc0) matches the value set in the timer register ta0reg or when 2 n counter overflow occurs (n = 6, 7 or 8 as specified by ta01mod). the up counter uc0 is cleared when 2 n counter overflow occurs. the following conditions must be satisfied before this pwm mode can be used. value set in ta0reg < value set for 2 n counter overflow value set in ta0reg 0 figure 6-11 8-bit pwm waveforms figure 6-12 shows a block diagram representing this mode. figure 6-12 block diagr am of 8-bit pwm mode in this mode, the value of the register buffer will be shifted into ta0reg if 2 n overflow is detected when the ta0reg double buffer is enabled. ta1out t pwm ta0reg and  uc0 match 2 n overflow (intta0 interrupt) (pwm cycle) selector selector shift trigger comparator register buffer0 internal data bus ta01run ta0reg-wr 8-bit up counter (uc0) ta1ff ta1out intta0 ta1ffcr ta01mod ta01mod ta01run invert ta0in t1 t4 t16 ta0reg clear overflow 2 n overflow control
page 119 2007-10-15 tmp91fw60 use of the double buffer facilitates the handling of low duty ratio waves. figure 6-13 operation of register buffer 0 example: to output the following pwm waves on the ta1out pin at fc = 20 mhz: to achieve a 51.2 s pwm cycle by setting t1 to 2 3 /fc s (at fc = 20 mhz): 51.2 s/(2 3 /fc) s P 128 = 2 n therefore n should be set to 7. since the low-level period is 29.6 s when t1 = 2 3 /fc s (at fc = 20 mhz), set the following value for ta0reg: 29.6 s/(2 3 /fc) s P 74 = 4ah note:x : don't care ? : no change * clock state system clock : high frequency (fc) prescaler clock : f fph clock gear : 1 (fc) msb lsb 76543210 ta01run ?xxx???0stop tmra0 and clear it to 0. ta01mod 1110??01 select 8-bit pwm mode (cycle: 2 7 ) and select t1 as the input clock. ta0reg 01001010write 4ah. ta1ffcr xxxx1 0 1xclear ta1ff to 0, e nable the inversion and double buffer. p7cr xxx???1? set p71 and the ta1out pin. p7fc xxx???1? ta01run 1xxx?1?1start tmra0 counting. q 2 q 1 2 n overflow ta0reg (value to be compared) q 3 q 2 register buffer 0 shift into ta0reg ta0reg (register buffer 0) write (up counter = q 1 ) (up counter = q 2 ) match with ta0reg
page 120 2007-10-15 tmp91fw60 note: xxx: don't care 6.4.5 settings for each mode table 6-4 shows the sfr settings for each mode. note: ? : don?t care table 6-3 pwm cycle @ fc = 20 m hz, fs = 32.768 khz select sys- tem clock syscr1 gear value syscr1 select prescaler clock syscr0 pwm cycle 2 6 2 7 2 8 t1 t4 t16 t1 t4 t16 t1 t4 t16 1 (fs) xxx 0 (1/1) f fph 15.6 ms 62.5 ms 250 ms 31.3 ms 125 ms 500 ms 62.5 ms 250 ms 1000 ms 0 (fc) 000 (fc) 25.6 s102.4 s 409.6 s51.2 s 204.8 s819.2 s 102.4 s 409.6 s 1638 s 001 (fc/2) 51.2 s204.8 s 819.2 s102.4 s 409.6 s 1638 s 204.8 s 819.2 s 3277 s 010 (fc/4) 102.4 s409.6 s 1638 s204.8 s 810.2 s 3277 s 409.6 s 1638 s 6554 s 011 (fc/8) 204.8 s819.2 s 3277 s409.6 s 1638 s 6554 s 819.2 s 3277 s 13107 s 100 (fc/16) 409.6 s 1638 s 6554 s819.2 s 3277 s 13107 s 1638 s 6554 s 26214 s xxx 1 (1/16) fc/16 clock 409.6 s 1638 s 6554 s819.2 s 3277 s 13107 s 1638 s 6554 s 26214 s table 6-4 timer mode setting registers register name ta01mod ta1ffcr ta1ffis function timer mode pwm cycle upper timer input clock lower timer input clock timer f/f invert signal select 8-bit timer 2 channels 00 ? lower timer match t1, t16, t256 (00, 01, 10, 11) external clock t1 t4, t16 (00, 01, 10, 11) 0: lower timer output 1: upper timer output 16-bit timer mode 01 ? ? external clock t1, t4, t16 (00, 01, 10, 11) ? 8-bit ppg 1 channel 10 ? ? external clock t1, t4, t16 (00, 01, 10, 11) ? 8-bit pwm 1 channel 11 2 6 , 2 7 , 2 8 (01, 10, 11) ? external clock t1, t4, t16 (00, 01, 10, 11) ? 8-bit timer 1 channel 11 ? t1, t16, t256 (01, 10, 11) ? output disabled
page 121 2007-10-15 tmp91fw60 7. 16-bit timer/event counters (tmrb) the tmp91fw60 incorporates five multifunctional 16 -bit timer/event counters (tmrb0, tmrb1, tmrb2, tmrb3, tmrb4) which have the following operation modes: ? 16-bit interval timer mode ? 16-bit event counter mode ? 16-bit programmable pulse generation (ppg) output mode the capture function enables selection of the following modes: ? frequency measurement mode ? pulse width measurement mode ? time differential measurement figure 7-1 show block diagrams fo r tmrb0, tmrb1, tmrb2, tmrb3 and tmrb4. each timer/event counter channel consists of a 16-bit up-c ounter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, two timer flip- flops and a timer flip-flop controller. each timer/event counter is controlled by an 11-byte sfr (special-function register). each of the five channels (tmrb0, tmrb1, tm rb2, tmrb3, tmrb4) can be used independently. each chan- nel features the same operations except for those describe d in table 7-1. hence, only the operation of tmrb0 is explained below. table 7-1 registers and pins for tmrb channel tmrb0 tmrb1 tmrb2 tmrb3 tmrb4 specification external pins external clock/capture trigger input pins tb0in0 (also used as p80) tb1in0 (also used as p84) tb2in0 (also used as pa0) tb3in0 (also used as p30) tb4in0 (also used as pb0) tb0in1 (also used as p81) tb1in1 (also used as p85) tb2in1 (also used as pa1) tb3in1 (also used as p31) tb4in1 (also used as pb1) timer flip-flop output pins tb0out0 (also used as p82) tb1out0 (also used as p86) tb2out0 (also used as pa2) tb3out0 (also used as p32) tb4out0 (also used as pb2) tb0out1 (also used as p83) tb1out1 (also used as p87) tb2out1 (also used as pa3) tb3out1 (also used as p33) tb4out1 (also used as pb3) sfr (address) timer run register tb0run (0180h) tb1run (0190h) tb2run (01a0h) tb3run (01b0h) tb4run (01c0h) timer mode register tb0mod (0182h) tb1mod (0192h) tb2mod (01a2h) tb3mod (01b2h) tb4mod (01c2h) timer flip-flop control register tb0ffcr (0183h) tb1ffcr (0193h) tb2ffcr (01a3h) tb3ffcr (01b3h) tb4ffcr (01c3h) timer registers tb0rg0l (0188h) tb1rg0l (0198h) tb2rg0l (01a8h) tb3rg0l (01b8h) tb4rg0l (01c8h) tb0rg0h (0189h) tb1rg0h (0199h) tb2rg0h (01a9h) tb3rg0h (01b9h) tb4rg0h (01c9h) tb0rg1l (018ah) tb1rg1l (019ah) tb2rg1l (01aah) tb3rg1l (01bah) tb4rg1l (01cah) tb0rg1h (018bh) tb1rg1h (019bh) tb2rg1h (01abh) tb3rg1h (01bbh) tb4rg1h (01cbh) capture registers tb0cp0l (018ch) tb1cp0l (019ch) tb2cp0l (01ach) tb3cp0l (01bch) tb4cp0l (01cch) tb0cp0h (018dh) tb1cp0h (019dh) tb2cp0h (01adh) tb3cp0h (01bdh) tb4cp0h (01cdh) tb0cp1l (018eh) tb1cp1l (019eh) tb2cp1l (01aeh) tb3cp1l (01beh) tb4cp1l (01ceh) tb0cp1h (018fh) tb1cp1h (019fh) tb2cp1h (01afh) tb3cp1h (01bfh) tb4cp1h (01cfh)
page 122 2007-10-15 tmp91fw60 7.1 block diagrams figure 7-1 block diagrams of tmrb0 to tmrb4  timer flip-flop control  capture, external int input control 16-bit comparator (cpn1) 16-bit  timer register tbnrg1h/l 16-bit comparator (cpn0) capture register 0 tbncp0h/l 2 4 8 16 32 intx inty
t t1
t t4
t t16
t t1
t t4
t t16 tazout tbnin0 tbnin1 run/ clear tbnrun tbnmod tbnrun tbnmod tbnmod tbnrun tbnmod inttbn0 inttbn1 tbnout1 capture register 1 tbncp1h/l 16-bit  timer register tbnrg0h/l  register buffer p tbnff0 tbnff1  16-bit up-counter (ucn) match detection timer n intx inty tazout internal data bus internal data bus int output timer flip-flop output tbnout0 overflow interrupt  inttbofn timer flip-flop match detection  prescaler clock:
t t0 external int input (from tmra) selector count clock internal data bus internal data bus tmrb0 0 int5 int6 ta1out tmrb1 1 int7 int8 ta1out tmrb2 2 int1 int2 ta1out tmrb3 3 int3 int4 ta3out tmrb4 4 int9 int10 ta5out
page 123 2007-10-15 tmp91fw60 7.2 operation of each block 7.2.1 prescaler the 5-bit prescaler generates the source clock for tmrb0. the prescaler clock ( t0) is divided clock (divided by 4) from select ed clock by the register syscr0 of clock gear. this prescaler can be started or stopped using tb0run. counting starts when is set to 1; the prescaler is cleared to 0 and stops operation when is cleared to 0. table 7-2 show prescaler output clock resolution. note: xxx: don?t care 7.2.2 up counter (uc0) uc0 is a 16-bit binary counter which counts up according to input from the clock specified by tb0mod register. as the input clock, one of th e prescaler internal clocks t1, t4 and t16 or an external clock from tb0in0 pin can be selected. counting or stopping and clearing of the counter is controlled by timer operation control register tb0run. when clearing is enabled, the up co unter uc0 will be cleared to 0 each time its value matches the value in the timer register tb0rg1h/l. if cl earing is disabled, the counter operate s as a free-running counter. clearing can be enabled or disabled by using tb0mod. a timer overflow interrupt (inttbof0) is generated when uc0 overflow occurs. 7.2.3 timer registers (tb0rg0h/l, tb0rg1h/l) these two 16-bit registers are used to set the interval time. when the value in the up counter uc0 matches the value set in this timer register, the comparator match detect signal will go active. setting data for both upper and lower timer registers is needed. for example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twic e for lower 8 bits and upper 8 bits in order. (the com- pare circuit will not operate if only the lower 8 bits are written. be sure to write to both timer registers (16 bits) from the lower 8 bits followed by the upper 8 bits.) the tb0rg0h/l timer register has a double-buffer struct ure, which is paired with register buffer 0. the value set in tb0run determines whether the do uble-buffer structure is en abled or disabled: it is disabled when = "0", and enabled when = "1". table 7-2 prescaler output clock resolution @fc = 20 mhz, fs = 32.768 khz system clock selectionsysc1< sysck> clock gear value syscr1 prescaler clock selection prescaler output clock resolution t1 (1/2) t4 (1/8) t16 (1/32) 1 (fs) xxx 0 (1/1) f fph 2 3 /fs (244 s) 2 5 /fs (977 s) 2 7 /fs (3.9 ms) 0 (fc) 000 (fc) 2 3 /fc (0.4 s) 2 5 /fc (1.6 s) 2 7 /fc(6.4 s) 001 (fc/2) 2 4 /fc (0.8 s) 2 6 /fc (3.2 s) 2 8 /fc (12.8 s) 010 (fc/4) 2 5 /fc (1.6 s) 2 7 /fc (6.4 s) 2 9 /fc (25.6 s) 011 (fc/8) 2 6 /fc (3.2 s) 2 8 /fc (12.8 s) 2 10 /fc (51.2 s) 100 (fc/16) 2 7 /fc (6.4 s) 2 9 /fc (25.6 s) 2 11 /fc (102.4 s) xxx 1 (1/16) fc/16 clock 2 7 /fc (6.4 s) 2 9 /fc (25.6 s) 2 11 /fc (102.4 s)
page 124 2007-10-15 tmp91fw60 when the double buffer is enabled, data is transferred from the register buffer 0 to the timer register when the values in the up counter (uc0) and the timer register tb0rg1h/l match. the double buffer circuit incorporates two flags to indicate whether or not data is written to the lower 8 bits and the upper 8 bits of the register buffer, respectively. only when both fl ags are set can data be transferred from the register buffer to the tim er register by a match between the up-counter uc0 and the timer register tb0rg1. this data transfer is performed so long as 16-bit da ta is written in the register buffer regardless of the register buffer to the timer register unexpectedly as explained below. for example, let us assume that an in terrupt occurs when only the lower 8 bits (l1) of the register buffer data (h1l1) have been written and the inte rrupt routine includes writes to all 16 bits in the register buffer and a transfer of the data to the timer register. in this case, if the higher 8 bits (h1) are written after the interrupt rou- tine is completed, only the flag for the higher 8 bits will be set, the flag for the lower 8 bits having been cleared in the interrupt routine. therefore, even if a match occurs between uc0 and tb0rg1 , no data transfer will be performed. then, in an attempt to set the next set of data (h2l2) in the register buffer, when the lower 8 bits (l2) are written, this will cause the flag for the lower 8 bits to be set as well as the flag for the higher 8 bits which has been set by writing the previous data (h1). if a matc h between uc0 and tb0rg1 occurs before the higher 8 bits (h2) are written, this will cause unexpected data (h1l2) to be sent to the timer register instead of the intended data (h2l2). to avoid such transfer timing problems due to interrupt s, the di instruction (disable interrupts) and the ei (enable interrupts) can be executed before and after setting data in the register buffer, respectively. after a reset, tb0rg0h/l and tb0rg1h/l are undefined. if the 16-bit timer is to be used after a reset, data should be written to it beforehand. on a reset is initialized to "0", disabling the double buffer. to use the double buffer, write data to the timer register, set to "1", then write data to the register buffer 10 as shown below. tb0rg0h/l and the register buffer 0 both have the same memory addresses (0188h and 0189h) allocated to them. if = "0", the value is written to both the timer register and the register buffer 0. if = "1", the value is writt en to the register buffer 0 only. the addresses of the timer registers are as follows: note:the timer registers are write- only registers and thus cannot be read. tmrb0 tb0rg0h/l tb0rg1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 000189h 000188h 00018bh 00018ah tmrb1 tb1rg0h/l tb1rg1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 000199h 000198h 00019bh 00019ah tmrb2 tb2rg0h/l tb2rg1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 0001a9h 0001a8h 0001abh 0001aah tmrb3 tb3rg0h/l tb3rg1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 0001b9h 0001b8h 0001bbh 0001bah tmrb4 tb4rg0h/l tb4rg1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 0001c9h 0001c8h 0001cbh 0001cah
page 125 2007-10-15 tmp91fw60 7.2.4 capture registers (tb0cp0h/l, tb0cp1h/l) these 16-bit registers are used to latc h the values in th e up counter (uc0). data in the capture registers should be read all 16 bits . for example, using a 2-byte data load instruction or two 1-byte data load instructions. the least significant byte is read first, followed by the most significant byte. (during capture is read, capture operati on is prohibited. in that case, the lowe r 8 bits should be read first, fol- lowed by the 8 bits.) the addresses of the capture registers are as follows; note:the capture registers are read-only registers and thus cannot be written to. 7.2.5 capture input control and external interrupt control this circuit controls the timing to latch the value of up-counter uc0 into tb0cp0h/l and tb0cp1h/l, and generates external interrupt.the latch timing of capture re gister and selection of edge for external interrupt is controlled by tb0mod. the value in the up-counter (uc0) can be loaded into a capture register by software. whenever 0 is written to tb0mod, the current valu e in the up counter (uc0) is load ed into capture register tb0cp0h/ l. it is necessary to keep the prescaler in run mode (e.g., tb0run must be held at a value of 1). tmrb0 tb0cp0h/l tb0cp1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 00 018d h00 018c h 00 018f h00 018e h tmrb1 tb1cp0h/l tb1cp1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 00 019d h00 019c h 00 019f h00 019e h tmrb2 tb2cp0h/l tb2cp1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 00 01ad h00 01ac h 00 01af h00 01ae h tmrb3 tb3cp0h/l tb3cp1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 00 01bd h00 01bc h 00 01bf h00 01be h tmrb4 tb4cp0h/l tb4cp1h/l upper 8 bits lower 8 bits upper 8 bits lower 8 bits 00 01cd h00 01cc h 00 01cf h00 01ce h
page 126 2007-10-15 tmp91fw60 7.2.6 comparators (cp00, cp01) cp10 and cp11 are 16-bit comparators which compare the value in the up counter uc0 with the value set in tb0rg0h/l or tb0rg1h/l respectively, in order to det ect a match. if a match is detected, the comparator generates an interrupt (inttb00 or inttb01 respectively) . 7.2.7 timer flip-flops (tb0ff0, tb0ff1) these flip-flops are inverted by the match detect si gnals from the comparators a nd the latch signals to the capture registers. inversion can be enabled and disabled for each element using tb0ffcr. after a reset the value of tb0ff0 is undefined. if "00" is written to tb0ffcr or , tb0ff0 will be inverted . if "01" is written to the capture registers, the value of tb0ff0 will be set to "1". if "10" is written to the capture registers, the value of tb0ff0 will be set to "0". note:if an inversion by the match-detect signal and a se tting change via the tb0ffcr register occurs simulta- neously, the resultant operation varies depending on the situation, as shown below. ? if an inversion by the match-detect si gnal and an inversion via the register oc cur simultaneously, the flip-flop will be inverted only once. ? if an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur simultaneously, the flip-flop will be set to 1. ? if an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur simulta- neously, the flip-flop will be cleared to 0. if an inversion by match-detect signal and inversion disable setting occur simult aneously, two case (it is inverted and it is not inverted) are occurred. therefore, if changing inve rsion control (inversion enable/ disable), stop timer operation beforehand. the values of tb0ff0 and tb0ff1 can be output via th e timer output pins tb0out0 (which is shared with p82 and tb0out1 (which is shared with p83). timer output should be specified using the port p function reg- ister.
page 127 2007-10-15 tmp91fw60 7.3 sfr note: bits 1, 4 and 5 of tb0run/tb1run/tb2run/tb3run/tb4run are "1" when read. tmrb run register 76543210 tb0run (0180h) bit symbol tb0rde ? ? ? i2tb0 tb0prun ? tb0run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 0 0 ? 0 function double buffer 0: disable 1: enable always write 0. not in use idle2 0: stop 1: operate tmrb0 prescaler uc0 0: stop and clear 1: run (count up) tb1run (0190h) bit symbol tb1rde ? ? ? i2tb1 tb1prun ? tb1run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 0 0 ? 0 function double buffer 0: disable 1: enable always write 0. not in use idle2 0: stop 1: operate tmrb1 prescaler uc1 0: stop and clear 1: run (count up) tb2run (01a0h) bit symbol tb2rde ? ? ? i2tb2 tb2prun ? tb2run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 0 0 ? 0 function double buffer 0: disable 1: enable always write 0. not in use idle2 0: stop 1: operate tmrb2 prescaler uc2 0: stop and clear 1: run (count up) tb3run (01b0h) bit symbol tb3rde ? ? ? i2tb3 tb3prun ? tb3run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 0 0 ? 0 function double buffer 0: disable 1: enable always write 0. not in use idle2 0: stop 1: operate tmrb3 prescaler uc3 0: stop and clear 1: run (count up) tb4run (01c0h) bit symbol tb4rde ? ? ? i2tb4 tb4prun ? tb4run read/write r/w r/w ? ? r/w r/w ? r/w after reset 0 0 0 0 ? 0 function double buffer 0: disable 1: enable always write 0. not in use idle2 0: stop 1: operate tmrb4 prescaler uc4 0: stop and clear 1: run (count up) operation i2tb0, i2tb1, i2tb2, i2tb3, i2tb4: operation of idle2 mode 0 stop and clear tb0prun, tb1prun, tb2p run, tb3prun, tb4prun: operation of prescaler 1 count tb0run, tb1run, tb2 run, tb3run, tb4run: operation of tmrb
page 128 2007-10-15 tmp91fw60 tmrb mode register (read-modify-write instructions are prohibited.) (1/2) 76 5 4 3 210 tb0mod (0182h) bit symbol tb0ct1 tb0et1 tb0cp0i tb0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 read/write r/w w* r/w after reset 0 0 1 0 0 0 0 0 function tb0ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: undefined capture timing 00: disable int5 occurs at rising edge 01: tb0in0 tb0in1 int5 occurs at rising edge 10: tb0in0 tb0in0 int5 occurs at falling edge 11: ta1out ta1out int5 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb0 input clock select 00: tb0in0 pin input 01: t1 10: t4 11: t16 invert when uc0 is loaded into tb0cp1h/l invert when uc0 matches with tb0rg1h/l tb1mod (0192h) bit symbol tb1ct1 tb1et1 tb1cp0i tb1cpm1 tb1cpm0 tb1cle tb1clk1 tb1clk0 read/write r/w w* r/w after reset 0 0 1 0 0 0 0 0 function tb1ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: undefined capture timing 00: disable int7 occurs at rising edge 01: tb1in0 tb1in1 int7 occurs at rising edge 10: tb1in0 tb1in0 int7 occurs at falling edge 11: ta1out ta1out int7 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb1 input clock select 00: tb1in0 pin input 01: t1 10: t4 11: t16 invert when uc1 is loaded into tb1cp1h/l invert when uc1 matches with tb1rg1h/l tb2mod (01a2h) bit symbol tb2ct1 tb2et1 tb2cp0i tb2cpm1 tb2cpm0 tb2cle tb2clk1 tb2clk0 read/write r/w w* r/w after reset 0 0 1 0 0 0 0 0 function tb2ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: undefined capture timing 00: disable int1 occurs at rising edge 01: tb2in0 tb2in1 int1 occurs at rising edge 10: tb2in0 tb2in0 int1 occurs at falling edge 11: ta1out ta1out int1 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb2 input clock select 00: tb2in0 pin input 01: t1 10: t4 11: t16 invert when uc2 is loaded into tb2cp1h/l invert when uc2 matches with tb2rg1h/l tb3mod (01b2h) bit symbol tb3ct1 tb3et1 tb3cp0i tb3cpm1 tb3cpm0 tb3cle tb3clk1 tb3clk0 read/write r/w w* r/w after reset 0 0 1 0 0 0 0 0 function tb3ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: undefined capture timing 00: disable int3 occurs at rising edge 01: tb3in0 tb3in1 int3 occurs at rising edge 10: tb3in0 tb3in0 int3 occurs at falling edge 11: ta3out ta3out int3 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb3 input clock select 00: tb3in0 pin input 01: t1 10: t4 11: t16 invert when uc3 is loaded into tb3cp1h/l invert when uc3 matches with tb3rg1h/l
page 129 2007-10-15 tmp91fw60 note 1: n=0,1,2,3,4 note 2: z=1,3,5 note 3: as described above, whenever 0 is written to tbnmod, the current value in the up counter is loaded into cap- ture register tbncp0h/l. however, note that the current value in the up counter is also loaded into capture register tbncp0h/l when 1 is written to tbnmod while this bit is holding 0. tmrb mode register (read-modify-write instructions are prohibited.) (2/2) 76 5 4 3 210 tb4mod (01c2h) bit symbol tb4ct1 tb4et1 tb4cp0i tb4cpm1 tb4cpm0 tb4cle tb4clk1 tb4clk0 read/write r/w w* r/w after reset 0 0 1 0 0 0 0 0 function tb4ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: undefined capture timing 00: disable int9 occurs at rising edge 01: tb4in0 tb4in1 int9 occurs at rising edge 10: tb4in0 tb4in0 int9 occurs at falling edge 11: ta5out ta5out int9 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb4 input clock select 00: tb4in0 pin input 01: t1 10: t4 11: t16 invert when uc4 is loaded into tb4cp1h/l invert when uc4 matches with tb4rg1h/l tmrb source clock 00 external input clock (tbnin0 pin input) 01 t1 10 t4 11 t16 up counter clear control (ucn) 0 disable to clear up counter 1 clear by match with tbnrg1h/l capture/interrupt timing capture control int5 control 00 disable capture int generate at ris- ing edge of tbnin0 01 capture to tbncp0h/l at rising edge of tbnin0 capture to tbncp1h/l at rising edge of tbnin1 10 capture to tbncp0h/l at rising edge of tbnin0 capture to tbncp1h/l at falling edge of tbnin0 int generate at fall- ing edge of tbnin0 11 capture to tbncp0h/l at rising edge of tazout capture to tbncp1h/l at falling edge of tazout int generate at ris- ing edge of tbnin0 software capture 0 capture value of up counter to tbncp0h/l. 1 undefined (note 3)
page 130 2007-10-15 tmp91fw60 tmrb flip-flop control register (read-modify-w rite instructions are prohibited.) (1/2) 76543210 tb0ffcr (0183h) bit symbol tb0ff1c1 tb0ff1c0 tb0c1t1 tb0 c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 read/write w* r/w w* after reset11000011 function tb0ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb0ff0 inversion trigger 0: disable 1: enable tb0ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc0 is loaded into tb0cp1h/l. invert when uc0 is loaded into tb0cp0h/l. invert when uc0 matches tb0rg1h/l. invert when uc0 matches tb0rg0h/l. tb1ffcr (0193h) bit symbol tb1ff1c1 tb1ff1c0 tb1c1t1 tb1 c0t1 tb1e1t1 tb1e0t1 tb1ff0c1 tb1ff0c0 read/write w* r/w w* after reset11000011 function tb1ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb1ff0 inversion trigger 0: disable 1: enable tb1ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc1 is loaded into tb1cp1h/l. invert when uc1 is loaded into tb1cp0h/l. invert when uc1 matches tb1rg1h/l. invert when uc1 matches tb1rg0h/l. tb2ffcr (01a3h) bit symbol tb2ff1c1 tb2ff1c0 tb2c1t1 tb2 c0t1 tb2e1t1 tb2e0t1 tb2ff0c1 tb2ff0c0 read/write w* r/w w* after reset11000011 function tb2ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb2ff0 inversion trigger 0: disable 1: enable tb2ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc2 is loaded into tb2cp1h/l. invert when uc2 is loaded into tb2cp0h/l. invert when uc2 matches tb2rg1h/l. invert when uc2 matches tb2rg0h/l. tb3ffcr (01b3h) bit symbol tb3ff1c1 tb3ff1c0 tb3c1t1 tb3c0t1 tb3e1t1 tb3e0t1 tb3ff0c1 tb3ff0c0 read/write w* r/w w* after reset11000011 function tb3ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb3ff0 inversion trigger 0: disable 1: enable tb3ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc3 is loaded into tb3cp1h/l. invert when uc3 is loaded into tb3cp0h/l. invert when uc3 matches tb3rg1h/l. invert when uc3 matches tb3rg0h/l.
page 131 2007-10-15 tmp91fw60 note: n=0,1,2,3,4 tmrb flip-flop control register (read-modify-w rite instructions are prohibited.) (2/2) 76543210 tb4ffcr (01c3h) bit symbol tb4ff1c1 tb4ff1c0 tb4c1t1 tb4 c0t1 tb4e1t1 tb4e0t1 tb4ff0c1 tb4ff0c0 read/write w* r/w w* after reset11000011 function tb4ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb4ff0 inversion trigger 0: disable 1: enable tb4ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc4 is loaded into tb4cp1h/l. invert when uc4 is loaded into tb4cp0h/l. invert when uc4 matches tb4rg1h/l. invert when uc4 matches tb4rg0h/l. timer flip-flop (tbnff0) control 00 invert tbnff0. 01 set tbnff0 to 1. 10 clear tbnff0 to 0. 11 don?t care tbnff0 inversion when ucn matches tbnrg0h/l 0 disable trigger (disable inversion). 1 enable trigger (enable inversion). tbnff0 inversion when ucn matches tbnrg1h/l 0 disable trigger (disable inversion). 1 enable trigger (enable inversion). tbnff0 inversion when ucn is loaded into tbncp0h/l 0 disable trigger (disable inversion). 1 enable trigger (enable inversion). tbnff0 inversion when ucn is loaded into tbncp1h/l 0 disable trigger (disable inversion). 1 enable trigger (enable inversion). timer flip-flop (tbnff1) control 00 invert tbnff1. 01 set tbnff1 to 1. 10 clear tbnff1 to 0. 11 don?t care
page 132 2007-10-15 tmp91fw60 7.4 operation in each mode 7.4.1 16-bit interval timer mode generating interrupts at fixed intervals in this example the interrupt inttb01 is set to be generated at fixed intervals. the interval time is set in the timer register tb0rg1h/l. note:x: don't care, ?: no change 7.4.2 16-bit ev ent counter mode if the external clock (tb0in0 pin in put) is selected as the input clock in 16-bit timer mode, the timer can be used as an event counter. the up-counter counts up on the rising edge of tb0in0 input. to read the value of the counter, first perform software captu re once, then read the captured value. note 1: x: don't care, ?: no change note 2: when the timer is used as an event counter, set the prescaler to run mode (tb0run = 1). 76543210 tb0run 0 0 x x ? 0 x 0 stop tmrb0. intetb0 x 1 0 0 x 0 0 0 enable inttb01 and set it to interrupt level 4. disable inttb00. tb0ffcr 11000011disable trigger. tb0mod 001001* * select internal clock for input and disable the capture function. (**=01, 10, 11) tb0rg1 ********set interval time (16 bits). ******** tb0run 00xx?1x1start tmrb0. 6543210 tb0run 0 0 x x ? 0 x 0 stop tmrb0. p8cr ???????0set port to input mode. p8fc ???????1set port to input mode. intetb0 x 1 0 0 x 0 0 0 enable inttb01 and set interrupt level 4. disable inttb00. tb0ffcr 11000011disable trigger. tb0mod 0 0 1 0 0 1 0 0 select tb0in0 as the input clock. tb0rg1 ********set the number of counts (16 bits). ******** tb0run 00xx?1x1start tmrb0.
page 133 2007-10-15 tmp91fw60 7.4.3 16-bit programmable puls e generation (ppg) output mode square wave pulses can be generated at any frequency and duty ratio. the output pulse may be either active- low or active-high. in ppg mode a match between the value of the up-c ounter uc0 and either tim er register tb0rg0 or tb0rg1 inverts the output value for timer flip-flop tb0ff0. the tb0ff0 output value is output on tb0out0. in this mode the follow ing conditions must be satisfied. (value set in tb0rg0) < (value set in tb0rg1) figure 7-2 programmable pulse generati on (ppg) output waveforms when the tb0rg0 double buffer is enabled in this mode, the value of register buffer 0 will be shifted into tb0rg0 when the up-counter value matches tb0rg1. this feature facilitates the handling of low-duty waves. figure 7-3 operatio n of register buffer note:the values that can be set in tbxrgx range from 0001h to 0000h (equivalent to 10000h). if the maximum value 0000h is set, the match-detect signal goes active when the up-counter overflows. tb0out0 pin match with tb0rg0 (inttb00 interrupt) match with tb0rg1 (inttb01 interrupt) q 2 q 1 match with tb0rg1 tb0rg0 (value to be compared) q 3 q 2 register buffer shift into tb0rg1 write to tb0rg0 up-counter = q 1 up-counter = q 2 match with tb0rg0
page 134 2007-10-15 tmp91fw60 the following block diagram illustrates this mode. figure 7-4 block diagram of 16-bit ppg mode the following example shows how to set 16-bit ppg output mode: note:x: don?t care, ?: no change 76543210 tb0run 0 0 x x ? 0 x 0 disable the tb0rgh/l double buffer and stop tmrb0. tb0rg0 ********set the duty ratio. ********(16 bits) tb0rg1 ********set the fre quency. ********(16 bits) tb0run 10xx?0x0 enable the tb0rg0h/l double buffer. (the duty and frequency are changed on an inttb01 interrupt.) tb0ffcr 11001110 set the mode to invert tb0ff0 at the match with tb0rg0h/l, tb0rg1h/l. clear tb0ff0 to ?0?. tb0mod 001001* * select prescaler output as input clock and disable the capture func- tion. (**=01, 10, 11) p8cr ?????1?? set p82 to function as tb0out0. p8fc ?????1?? tb0run 10xx?1x1start tmrb0. 16 dkveqorctcvqt 4gikuvgtdwhhgt 0 16 dkveqorctcvqt tb0rg1h/l tb0run tb0rg0-wr 16-bit up counter (uc0) f/f (tb0ff0) tb0out0 (ppg qwvrwv ) tb0run tb0in0
t t1
t t4
t t16 tb0rg0h/l internal data bus selector selector match clear
page 135 2007-10-15 tmp91fw60 7.4.4 capture function examples used capture function, they can be ap plicable in many ways, for example: 1. one-shot pulse output from external trigger pulse 2. frequency measurement 3. pulse width measurement 4. time difference measurement 7.4.4.1 one-shot pulse output from external trigger pulse set the up counter uc0 in free-running mode with the internal input clock, input the external trigger pulse from tb0in0 pin, and load the value of up-c ounter into capture regist er tb0cp0h/l at the rise edge of the tb0in0 pin. when the interrupt int5 is generated at the rise edge of tb0in0 input, set the tb0cp0h/l value (c) plus a delay time (d) to tb0rg0h/l (= c + d), and set the above set value (c + d) plus a one-shot width (p) to tb0rg1h/l (= c + d + p). and, set ?11? to timer flip-flop control register tb0ffcr. set to trigger enable for be inverted timer flip-flop tb0ff0 by uc0 matching with tb0rg0h/l and with tb0rg1h/l. when interrupt inttb01 occurs, this inversion will be disabled after one-shot pulse is output. the (c), (d) and (p) correspond to c, d and p figure 7-5. figure 7-5 one-shot pu lse output (with delay) c p c + dc + d + p d count clock (prescaler output clock) timer output pin tb0out0 tb0in0 pin input (external trigger pulse) match with tb0rg0h/l match with tb0rg1h/l inversion enable inversion enable set the counter in free-running mode. load to capture register 0 (tb0cp0h/l) int5 occurred inttb01 occurred disables inversion caused by loading into tb0cp1h/l. pulse width delay time
page 136 2007-10-15 tmp91fw60 example: to output a 2-ms one-shot pulse with a 3-ms delay to the external trigger pulse to the tb0in0 pin. note: x: don't care, ?: no change when delay time is unnecessary, invert timer flip-flop tb0ff0 when up-counter value is loaded into capture register (tb0cp0h/l), and set the tb0cp0h/l value (c) plus the one-shot pulse width (p) to tb0rg1h/l when the interrupt int5 occurs. the tb0ff0 inversion should be enable when the up counter (uc10) value matches tb0rg1h/l, and disabled when generating the interrupt inttb01. figure 7-6 one-shot pulse out put (without delay) * clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph tb0mod xx101001 set free running. count with t1. load the up counter value into tb0cp0h/l at the rising edge of tb0in0 pin input. tb0ffcr xx000010clear tb0ff0 to 0. disable inversion of tb0ff0. p8cr ?????1?? set p82 to function as the tb0out0 pin. set p80 to tb0in0 input mode. p8fc ?????1?? inte56 x ? ? ? x 1 0 0 enable int5. intetb0 x 0 0 0 x 0 0 0 disable inttb00 and inttb01. tb0run ?0xx?1x1start tmrb0. tb0rg0 tb0cp0 + 3 ms/ t1 tb0rg1 tb0rg0 + 2 ms/ t1 tb0ffcr xx??11?? enable tb0ff0 inversion when the up counter value match with tb0rg0h/l or tb0rg1h/l. intetb0 x 1 0 0 x ? ? ? enable inttb01. tb0ffcr xx??00?? disable inversion of tb0ff0 when the up counter value match with value of tb0rg0h/l or tb0rg1h/l. intetb0 x 0 0 0 x ? ? ? disable inttb01. c p c + p count clock (prescaler output clock) timer output tb0out0 tb0in0 pin input (external trigger pulse) match with tb0rg1h/l inversion enable inttb01 occurred. enables inversion caused by loading into tb0cp0h/l. load into capture register 0 (tb0cp0h/l). int5 occurred. load the up counter value i n capture register 1 (tb0cp1 disable inversion caused by loading into tb0cp1h/l. pulse width
page 137 2007-10-15 tmp91fw60 7.4.4.2 frequency measurement the frequency of the external clock can be measur ed in this mode. the clock is input through the tb0in0 pin, and its frequency is measured by the 8-bit timers tmra01 and the 16-bit timer/event counter (tmrb0). (tmra01 is used to setting of measurement time by inversion ta1ff.) the tb0in0 pin input should be for the input clock of tmrb0. set to tb0mod = ?11?. the value of the up co unter (uc10) is loaded into the capture register tb0cp0h/l at the rise edge of the timer flip-flop ta1ff of 8-bit timers (t mra01), and into tb0cp1h/l at its fall edge. the frequency is calculated by difference between the loaded values in tb0cp0h/l and tb0cp1h/l when the interrupt (intta0 or intta1) is generates by either 8-bit timer. figure 7-7 fr equency measurement for example, if the value for the le vel 1 width of ta1ff of the 8-bit timer is set to 0.5 s and the differ- ence between the values in tb0cp0h/l and tb0cp1h/l is 100, the frequency is 100 0.5 s = 200 hz. note: the frequency in this exam ple is calculated with 50 duty. c1 c1 c1 c2 c2 c2 count clock (tb0in0 pin input) load to tb0cp1h/l ta1ff load to tb0cp0h/l intta0/intta1
page 138 2007-10-15 tmp91fw60 7.4.4.3 pulse width measurement this mode allows to measure the high-level width of an external pulse. while keeping the 16-bit timer/ event counter counting (free running) with the internal clock input, external pulse is input through the tb0in0 pin. then the capture function is used to load the uc0 values into tb0cp0h/l and tb0cp1h/l at the rising edge and fal ling edge of the external trigger pulse re spectively. the interr upt int5 occurs at the falling edge of tb0in0. the pulse width is obtained from the difference between the values of tb0cp0h/l and tb0cp1h/l and the internal clock cycle. for example, if the internal clock is 0.8 s and the difference between tb0cp0h/l and tb0cp1h/l is 100, the pulse width will be 100 0.8 s = 80 s. additionally, the pulse width which is over the uc0 maximum count time specified by the clock source, can be measured by changing software. figure 7-8 pulse width measurement note: only in this pulse width measuring mode (tb0mo d = 10), external interrupt int5 occurs at the falling edge of tb0in0 pin input. in other modes, it occurs at the rising edge. the width of low-level can be meas ured from the difference between th e first c2 and the second c1 at the second int5 interrupt. c1 c1 c1 c2 c2 c2 count clock (prescaler output clock) load to tb0cp1h/l tb0in0 pin input (external pulse) load to tb0cp0h/l int5
page 139 2007-10-15 tmp91fw60 7.4.4.4 time difference measurement this mode is used to measure the difference in time between the risi ng edges of external pulses input through tb0in0 and tb0in1. keep the 16-bit timer/event counte r (tmrb0) counting (free running) with the internal clock, and load the uc0 value into tb0cp0h/l at the rising edge of the input pulse to tb0in0. then the interrupt int5 is generated. similarly, the uc0 value is loaded into tb0cp1h/l at the rising edge of the input pulse to tb0in1, generating the interrupt int6. the time difference between these pulses can be obtained by multiplying the value subtracted tb0cp0h/l from tb0cp1h/l and the internal clock cycle together at which loading the up counter value into tb0cp0h/l and tb0cp1h/l has been done. figure 7-9 time difference measurement c1 c2 count clock (prescaler output clock) load to tb0cp1h/l tb0in0 pin input tb0in1 pin input load to tb0cp0h/l int5 int6 time difference
page 140 2007-10-15 tmp91fw60 8. serial channels (sio) tmp91fw60 includes 3 serial i/o channels. for both channels either uart mode (asynchronous transmission) or i/o interface mode (synchronous transmission) can be selected. 1. i/o interface mode ? mode 0: for transmitting and recei ving i/o data using the synchroni zing signal sclk for extending i/o. 2. uart mode ? mode 1: 7-bit data ? mode 1: 8-bit data ? mode 1: 9-bit data in mode 1 and mode 2, a parity bit can be added. mode 3 has a wakeup function for the master controller to start slave controllers via a serial li nk (a multi-controller system). figure 8-2 are block diagrams for each channel. sio is compounded mainly prescaler, serial clock generati on circuit, receiving buffer and control circuit, transmis- sion buffer and control circuit. both channels operate in the same function except for th e following points; hence only the operation of channel 0 is explained below. figure 8-1 data formats table 8-1 differences in se rial channel specifications sio0 sio1 sio2 pin name txd0 (p90) rxd0 (p91) cts0 /sclk0 (p92) txd1 (p93) rxd1 (p94) cts1 /sclk1 (p95) txd2 (p41) rxd2 (p42) cts 2 /sclk2 (p43) stop stop 1 bit 0 2 3 4 5 6 start bit 0 1 2 3 4 5 6 start bit 0 1 2 3 4 5 6 parity start bit 0 1 2 3 4 5 6 start bit 0 1 2 3 4 5 6 7 7 parity stop stop stop start bit 0 1 2 3 4 5 6 start bit 0 1 2 3 4 5 6 7 bit 8 7 8 stop 7 h  mode 0 (i/o interface mode  h  mode 1 (7-bit uart mode) transfer direction no parity parity h mode 2 (8-bit uart mode) no parity wakeup function h  mode 3 (9-bit uart mode  when bit8 = 1, address (select code) is denoted. when bit8 = 0, data is denoted. parity
page 141 2007-10-15 tmp91fw60 8.1 block diagrams figure 8-2 block diagram of the serial channel 0/1/2 0qvgp
5+15+15+1 transmission counter (uart only ? 16) receive counter (uart only ? 16) serial channel interrupt control transmission control selector prescaler selector selector selector 248163264
t t0 f sys
t t0
t t2
t t8
t t32
t t2
t t8
t t32 serial clock generation circuit baud date generator brncr ta0trg (from tmra0) brncr sc0cr sioclk scnmod0 scnmod0 txdclk scncr scnmod0 scnmod0 scnmod0 brncr brnadd prescaler uart mode sclkn sclkn rxdn txdn intrxn inttxn ? 2 error flag parity control rb8  receive buffer 1 (shift register) receive buffer 2 (scnbuf) tb8 transmission buffer (scnbuf) scncr i/o interface mode i/o interface mode receive control ctsn int request internal data bus rxdclk
page 142 2007-10-15 tmp91fw60 8.2 operation of each circuit 8.2.1 prescaler a 6-bit prescaler generates an operatio n clock for sio0. the prescaler is act eve only when a baud rate gener- ator is specified as a serial transfer clock. as an input clock of the prescaler, be sure to set syscr0 to ?0? and then specify f fph . this clock is used for t0 with being divided by 4. table 8-2 shows prescaler clock resolution into the baud rate generator. the baud rate generator selects between 4 clock inputs: t0, t2, t8, and t32 among the prescaler out- puts. 8.2.2 baud rate generator the baud rate generator is a circuit which generates transmission and receiving clocks which determine the transmission rate of the serial channels. the input clock to the baud rate generator, t0, t2, t8 or t32, is generated by the 6-bit prescaler which is shared by the timers. one of thes e input clocks is selected using the br0cr field in the baud rate generator control register. the baud rate generator includes a frequency divider, which divides the frequency by 1, n + (16 ? k)/16 or 16 values, determining the transmission rate. the tr ansmission rate is determined by the settings of br0cr and br0add. table 8-2 prescaler clock resolution to baud rate generator select system clock gear value select prescaler clock prescaler output clock resolution t0 t2 t8 t32 1 (fs) xxx 0 (1/1) f fph 2 2 /fs 2 4 /fs 2 6 /fs 2 8 /fs 0 (fc) 000 (fc) 2 2 /fc 2 4 /fc 2 6 /fc 2 8 /fc 001 (fc/2) 2 3 /fc 2 5 /fc 2 7 /fc 2 9 /fc 010 (fc/4) 2 4 /fc 2 6 /fc 2 8 /fc 2 10 /fc 011 (fc/8) 2 5 /fc 2 7 /fc 2 9 /fc 2 11 /fc 100 (fc/16) 2 6 /fc 2 8 /fc 2 10 /fc 2 12 /fc
page 143 2007-10-15 tmp91fw60 8.2.2.1 in uart mode (1) when br0cr = 0 the settings br0add are ignored. the baud rate generator divides the selected prescaler clock by n, which is set in br0ck. (n = 1, 2, 3 ... 16) (2) when br0cr = 1 the n + (16 ? k)/16 division function is enabled. the baud rate generator divides the selected prescaler clock by n + (16 ? k)/16 using the value of n set in br0cr (n = 2, 3 ... 15) and the value of k set in br0add (k = 1, 2, 3 ... 15) note: if n = 1 and n = 16, the n + (16 ? k)/16 division function is di sabled. set br0cr to ?0?. 8.2.2.2 in i/o interface mode the n + (16 ? k)/16 division fu nction is not available in i/o interface mode. se t br0cr to ?0? before dividing by n. the method for calculating the transm ission rate when the baud rate generator is used is explained below. (1) in uart mode (2) in i/o interface mode 8.2.2.3 integer divider (n divider) for example, when the source clock frequency (f c) =19.6608 mhz, the input clock frequency = t2 (fc/ 16), the frequency divider n ( br0cr) = 8, and br0cr = 0, the baud rate in uart mode is as follows: = 19.6608 10 6 16 8 16 = 9600 (bps) note: the + (16 - k)/16 division function is disabled and setting br0add is invalid . *clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph baud rate input clock of baud rate generator frequency divider for baud rate generator --------------------------------------------------------------------------------------------------- - 16 = baud rate input clock of baud rate generator frequency divider for baud rate generator --------------------------------------------------------------------------------------------------- - 2 = baudrate fc 16 ? 8 -------------- 16 =
page 144 2007-10-15 tmp91fw60 8.2.2.4 n + (16 - k)/16 divider (uart mode only) accordingly, when the source clock frequency (fc) = 15.9744 mhz, the input clock frequency = t2, the frequency divider n (br0cr) = 6, k (br0add) = 8, and br0cr = 1, the baud rate in uart mode is as follows: table 8-3 show examples of uart mode transfer rates. additionally, the external clock inpu t is available in the serial clock. the method for calculating the baud rate is explained below: ? in uart mode baud rate = external clock input frequency 16 it is necessary to satisfy (external clock input cycle) 4/f sys ? in i/o interface mode baud rate = external clock input frequency it is necessary to satisfy (external clock input cycle) 16/f sys note: transmission rates in i/o interface mode ar e eight times faster than the values given above. *clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph table 8-3 uart baud rate selection (when baud rate generator is used and br0cr=0, syscr0=0) unit (kbps) fc [mhz] input clock t0 (fc/4) t2 (fc/16) t8 (fc/64) t32 (fc/256) frequency divider n 7.3728 1 115.200 28.800 7.200 1.800 3 38.400 9.600 2.400 0.600 6 19.200 4.800 1.200 0.300 a 11.520 2.880 0.720 0.180 c 9.600 2.400 0.600 0.150 f 7.680 1.920 0.480 0.120 9.8304 1 153.600 38.400 9.600 2.400 2 76.800 19.200 4.800 1.200 4 38.400 9.600 2.400 0.600 5 30.720 7.680 1.920 0.480 8 19.200 4.800 1.200 0.300 10 9.600 2.400 0.600 0.150 baudrate= fc/16 6 16 8 ? () 16 ------------------- + ----------------------------- 16 ?? ?? ?? ?? 15.9744 10 6 16 6 8 16 ----- - + ?? ?? 16 = 9600(bps) =
page 145 2007-10-15 tmp91fw60 timer out clock (ta0trg) can be used for source clock of uart mode only. calculation method the frequency of ta0trg frequency of ta0trg = baud rate 16 note: in case of i/o interface mode, pr ohibit to use ta0trg for source clock. 8.2.3 serial clock generation circuit this circuit generates the basic clock for transmission and receiving data. 8.2.3.1 in i/o interface mode in sclk output mode with the setting sc0cr = ?0?, the basic clock is generated by dividing the output of the baud rate generato r by 2, as described previously. in sclk input mode with the setting sc0cr = ?1?, the rising edge or falling edge will be detected according to the setting of the sc0cr register to generate the basic clock. 8.2.3.2 in uart mode the sc0mod0 setting determines whether the baud rate generator clock, the internal system clock f sys , the match detect signal from timer tmra0 or th e external clock (sclk0) is used to generate the basic clock sioclk. 8.2.4 receiving counter the receiving counter is a 4-bit bina ry counter used in uart mode which counts up the pu lses of the sio- clk clock. it takes 16 sioclk pulses to receive 1 bit of data; each data bit is sampled three times ? on the 7th, 8th and 9th clock cycles. the value of the data bit is determined from these three samples using the majority rule. for example, if the data bit is samp led respectively as ?1?, ?0? and ?1? on 7th, 8th and 9th clock cycles, the received data bit is taken to be ?1?. a data bit sampled as ?0?, ?0? and ?1? is taken to be ?0?. 8.2.5 receiving control 8.2.5.1 in i/o interface mode in sclk output mode with the setting sc0cr = ?0?, the rxd0 signal is sampled on the rising or falling edge of the shift clock which is output on the sclk0 pin, according to the sc0cr setting. in sclk input mode with the setting sc0cr = ?1?, the rxd0 signal is sampled on the rising or falling edge of the sclk0 input, acco rding to the sc0cr setting. 8.2.5.2 in uart mode the receiving control block has a circuit which detect s a start bit using the majority rule. received bits are sampled three times; when two or more out of thr ee samples are ?0?, the bit is recognized as the start bit and the receiving operation commences. the values of the data bits that are received are also determined using the majority rule.
page 146 2007-10-15 tmp91fw60 8.2.6 receiving buffers to prevent overrun erro rs, the receiving buffers are arranged in a d ouble-buffer structure. received data is stored one bit at a time in r eceiving buffer 1 (which is a shift register). when 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transmitted to receiving buffer 2 (sc0buf); this causes an in trx0 interrupt to be generated. the cpu only reads receiving buffer 2 (sc0buf). even before the cpu reads receiving buffer 2 (sc0buf), the recei ved data can be stored in receiv- ing buffer 1. however, unless receiving buffer 2 (sc0buf) is read before a ll bits of the next data are received by receiving buffer 1, an overrun error occurs. if an overrun er ror occurs, the contents of receiving buffer 1 will be lost, although the conten ts of receiving buffer 2 a nd sc0cr will be preserved. sc0cr is used to store either the parity bit ? added in 8-bit uart mode ? or the most significant bit (msb) ? in 9-bit uart mode. in 9-bit uart mode the wakeup function for the slave controller is enabled by setting sc0mod0 to ?1?; in this mode intrx0 interrupts occur only when the value of sc0cr is ?1?. note 1: the double buffer structure does not support sc0cr. note 2: if the cpu reads receive buffer 2 while data is bei ng transferred from receive buffer 1 to receive buffer 2, the data may not be read properly. to avoid this situat ion, a read of receive buffer 2 should be triggered by a receive interrupt. 8.2.7 transmission counter the transmission counter is a 4-bit binary counter which is used in ua rt mode and which, like the receiv- ing counter, counts the sioclk clock pulses; a txdclk pulse is generated every 16 sioclk clock pulses. figure 8-3 generation of the transmission clock 8.2.8 transmission controller 8.2.8.1 in i/o interface mode in sclk output mode with the setting sc0cr = ?0?, the data in the transmission buffer is output one bit at a time to the txd0 pin on the rising or falling edge of the shift clock which is output on the sclk0 pin, according to the sc0cr setting. in sclk input mode with the setting sc0cr = ?1?, the data in the transmission buffer is output one bit at a time on the txd0 pin on the rising or falling edge of the sclk0 input, according to the sc0cr setting. 8.2.8.2 in uart mode when transmission data sent from the cpu is written to the transmission buffer, transmission starts on the rising edge of the next txdclk. sioclk txdclk 15161234567891011121314151612
page 147 2007-10-15 tmp91fw60 8.2.8.3 handshake function use of cts0 pin allows data can be sent in units of one frame; thus, overrun erro rs can be avoided. the handshake function is enabled or disabled by the sc0mod0 setting. when the cts0 pin goes high on completion of the current da ta send, data transmission is halted until the cts0 pin goes low again. however, the inttx0 interrup t is generated, it requests the next data send to the cpu. the next data is written in the tr ansmission buffer and data transmission is halted. though there is no rts pin, a handshake function can be easily configured by setting any port assigned to be the rts function. the rts should be output ?high? to request send data halt after data receive is completed by software in the rxd interrupt routine. figure 8-4 handshake function note 1: if the cts0 signal goes high during transmission, no more data will be sent after completion of the current transmission. note 2: transmission starts on the first falling edge of the txdclk clock after the cts0 signal has fallen. figure 8-5 cts0 (clear to send) timing txd cts0 rxd rts (any port) 6/2(9 6/2(9 sender receiver start bit bit 0 txd sioclk txdclk cts0 13 14 15 16 1 2 3 13 14 15 16 1 2 3 a b transmission is suspended during this period timing to write to the transmission buffer
page 148 2007-10-15 tmp91fw60 8.2.9 transmission buffer the transmission buffer (sc0buf) sh ifts out and sends the transmission data written from the cpu from the least significant bit (lsb) in order. when all the bits are shifted out, the transmission buffer becomes empty and generates an inttx0 interrupt. 8.2.10 parity control circuit when sc0cr in the serial channe l control register is set to ?1?, it is possible to transmit and receive data with parity. however, parity can be added only in 7-bit uart mode or 8-bit uart mode. the sc0cr field in the serial channe l control register allows either ev en or odd parity to be selected. in the case of transmission, parity is automatically gene rated when data is written to the transmission buffer sc0buf. the data is transmitted after the parity bit ha s been stored in sc0buf in 7-bit uart mode or in sc0mod0 in 8-bit uart mode. sc0cr and sc0cr must be set before the trans- mission data is written to the transmission buffer. in the case of receiving, data is shifte d into receiving buffer 1, and the pa rity is added after the data has been transmitted to receiving buffer 2 (sc0buf), and then compared with sc0buf in 7-bit uart mode or with sc0cr in 8-bit uart mode. if they are not equal, a parity error is generated and the sc0cr flag is set. 8.2.11 error flags three error flags are prov ided to increase the reli ability of data reception. 8.2.11.1 overrun error if all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 (sc0buf) , an overrun error is generated. the below is a recommended flow when the overrun error is generated. (intrx interrupt routine) 1. read receiving buffer 2. read error flag 3. if = 1 then a. set to disable receiving (w rite ?0? to sc0mod0) b. wait to termin ate current frame c. read receiving buffer d. read error flag e. set to enable receiving (write ?1? to sc0mod0) f. request to transmit again 4. other note: overrun errors are generated only with regard to receive buffer 2 (sc0buf). thus, if sc0cr is not read, no overrun error will occur.
page 149 2007-10-15 tmp91fw60 8.2.11.2 parity error the parity generated for the data sh ifted into receiving buffer 2 (sc0 buf) is compared with the parity bit received via the rxd pin. if they are not equal, a parity error is generated. note: the parity error flag is cleared every time it is r ead. however, if a parity error is detected twice in suc- cession and the parity error flag is read between the tw o parity errors, it may seem as if the flag had not been cleared. to avoid this situation, a read of t he parity error flag should be triggered by a receive interrupt. 8.2.11.3 framing error the stop bit for the received data is sampled three ti mes around the center. if th e majority of the samples are ?0?, a framing error is generated. 8.2.12 timing generation 8.2.12.1 in uart mode note 1: in 9 bits and 8 bits + parity mode, interrupts coincide with the ninth bit pulse. thus, when servicing the interrupt, it is nec- essary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. note 2: the higher the transfer rate, the later than the middle receive interrupts and errors occur. 8.2.12.2 i/o interface table 8-4 receiving mode 9 bits 8 bits + parity 8 bits, 7 bits + parity, 7 bits interrupt timing center of last bit (bit8) center of last bit (parity bit) center of stop bit framing error timing center of stop bit center of stop bit center of stop bit parity error timing ? center of last bit (parity bit) center of stop bit overrun error timing center of last bit (bit8) center of last bit (parity bit) center of stop bit table 8-5 transmitting mode 9 bits 8 bits + parity 8 bits, 7 bits + parity, 7 bits interrupt timing just before stop bit is trans- mitted just before stop bit is transmitted just before stop bit is transmitted transmission interrupt timing sclk output mode immediately after the last bit. (see figure 8-8) sclk input mode immediately after rise of last sclk signal rising mode, or immediately after fall in falling mode. (see figure 8-9) receiving interrupt timing sclk output mode timing used to transmit received data to receive buffer 2 (sc0buf) (e.g., immediately after last sclk). (see figure 8-10) sclk input mode timing used to transmit received data to receive buffer 2 (sc0buf) (e.g., immediately after last sclk). (see figure 8-11)
page 150 2007-10-15 tmp91fw60 8.3 sfr serial control register (read-modify-write instructions are prohibited.) 76543210 sc0cr (0201h) sc1cr (0209h) sc2cr (0211h) bit symbol rb8 even pe oerr perr ferr sclks ioc read/write r r/w r (cleared to "0" when read) r/w after resetundefined0000000 function received data bit8 parity 0: odd 1: even parity addi- tion 0: disable 1: enable overrun error flag 0: undetect error 1: detect error parity error flag 0: undetect error 1: detect error framing error flag 0: undetect error 1: detect error edge selec- tion for sclk pin (i/ o mode) 0: sclk 1: sclk i/o interface input clock selection 0: baud rate generator 1: sclk pin input note1: as all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. note2: a baud rate generator scncr = "0" is unavailable as an input clock for an i/o interface if a prescaler clock is set to fc/16 whensyscr0 is "1". note3: n =0, 1, 2. serial mode control register 0 76543210 sc0mod0 (0202h) sc1mod0 (020ah) sc2mod0 (0212h) bit symbol tb8 ctse rxe wu sm1 sm0 sc1 sc0 read/write r/w after reset00000000 function transmis- sion data bit8 handshake function 0: disable 1: enable receive function 0: disable 1: enable wakeup function 0: disable 1: enable serial transmission mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial transmission clock (uart) 00: timer ta0trg 01: baud rate generator 10: internal clock f sys 11: external clock (sclk input) note1: sclkpin and cts pin sclk pin cts pin sio0 sclk0 cts0 sio1 sclk1 cts1 sio2 sclk2 cts2 note2: a baud rate generator scnmod0 = "01" is unavai lable as a serial transfer clock if a prescaler clock is set to fc/16 whensyscr0 is "1". note3: n =0, 1, 2. serial mode control register 1 76543210 sc0mod1 (0205h) sc1mod1 (020dh) sc2mod1 (0215h) bit symboli2s0fdpx0?????? read/write r/w r/w ?????? after reset00?????? bit symboli2s1fdpx1?????? read/write r/w r/w ?????? after reset00?????? bit symboli2s2fdpx2?????? read/write r/w r/w ?????? after reset00?????? function idle2 0: stop 1: run duplex 0: half 1: full
page 151 2007-10-15 tmp91fw60 baud rate generator control 76543210 br0cr (0203h) bit symbol ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 read/write r/w after reset00000000 br1cr (020bh) bit symbol ? br1adde br1ck1 br1ck0 br1s3 br1s2 br1s1 br1s0 read/write r/w after reset00000000 br2cr (0213h) bit symbol ? br2adde br2ck1 br2ck0 br2s3 br2s2 br2s1 br2s0 read/write r/w after reset00000000 function always write ?0?. + (16 - k)/16 division 0: disable 1: enable input clock selection for baud rate generator 00: t0 01: t2 10: t8 11: t32 setting of the divided frequency ?n? 76543210 br0add (0204h) bit symbol ? ? ? ? br0k3 br0k2 br0k1 br0k0 read/write ? ? ? ? r/w after reset????0000 br1add (020ch) bit symbol ? ? ? ? br1k3 br1k2 br1k1 br1k0 read/write ? ? ? ? r/w after reset????0000 br2add (0214h) bit symbol ? ? ? ? br2k3 br2k2 br2k1 br2k0 read/write ? ? ? ? r/w after reset????0000 function sets frequency divisor ?k? (divided by n + (16 - k)/16) baud rate generator frequency divisor setting brncr = 1 brncr = 0 brncr 0000(n=16) or 0001(n=1) 0010(n=2) to 1111(n=15) 0001(n=1)uart only to 1111(n=15) 0000(n=16) brnadd 0000 disable disable divided by n 0001 (k = 1) disable divided by n + (16 - k)/ 16 to 1111 (k = 15) note: availability of +(16 - k)/16 division function n uart mode i/o mode the baud rate generator can be set ?1? in uart mode and disable + (16 - k)/16 division function. don?t use in i/o interface mode. 2 to 15 o x 1, 16 x x note: set br1cr to 1 after setting k (k = 1 to 15) to br1add when n+ (16 - k)/16 division function is used. note: n = 0,1,2
page 152 2007-10-15 tmp91fw60 8.4 operation in each mode 8.4.1 mode 0 (i/o interface mode) this mode allows an increase in the number of i/o pi ns available for transmittin g data to or receiving data from an external shift register. this mode includes the sclk output mode to output synchronous clock sclk and sclk input mode to input external synchronous clock sclk. figure 8-6 sclk output mode connection example figure 8-7 sclk inpu t mode connection example serial transmission/receiving buffer registers (read-modify-write instructions are prohibited.) 76543210 sc0buf (0200h) sc1buf (0208h) sc2buf (0210h) tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 (transmission) 76543210 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 (receiving) txd sclk port shift register  a b si c d sck e f rck g h rxd sclk port shift register  a  b qh c d clock e f s/l g h 6/2(9 6/2(9 output extension tc74hc595 or equivalent input extension tc74hc165 or equivalent txd sclk port rxd sclk port 6/2(9 6/2(9 output extension tc74hc595 or equivalent shift register a b si c d sck e f rck g h external clock input extension external clock tc74hc165 or equivalent shift register a b qh c d clock e f s/l g h
page 153 2007-10-15 tmp91fw60 8.4.1.1 transmission in sclk output mode 8-bit data and a synchronous clock are output on the txd0 and sclk0 pins respectively each time the cpu writes the data to the transmission buffer. when all data is output, intes0 will be set to generate the inttx0 interrupt. figure 8-8 transmitting operation in i/o interfac e mode (sclk output mode) in sclk input mode, 8-bit data is output on the txd0 pin when the sclk0 input becomes active after the data has been written to the transmission buff er by the cpu. when all data is output, intes0 will be set to generate inttx0 interrupt. figure 8-9 transmitting operation in i/o interfac e mode (sclk input mode) bit 0 bit 1 bit 6 bit 7 txd0 itx0c (inttx0 interrupt request) timing to write transmission data sclk0 output ( = 0: rising edge mode) sclk0 output ( = 1: falling edge mode) (internal clock timing) bit 0 bit 1 bit 5 bit 6 bit 7 sclk0 input ( = 1: falling edge mode) sclk0 input ( = 0: rising edge mode) txd0 itx0c (inttx0 interrupt request)
page 154 2007-10-15 tmp91fw60 8.4.1.2 receiving in sclk output mode, the synchronous clock is ou tputted from sclk0 pin and the data is shifted to receiving buffer 1. this starts when the receive in terrupt flag intes0 is cleared by reading the received data. when 8-bit data are received, the data will be transmitted to receiving buffer 2 (sc0buf according to the timi ng shown below) and intes0 will be set to generate intrx0 interrupt. the outputting for the first sclk0 starts by setting sc0mod0 to ?1?. figure 8-10 receiving op eration in i/o interfac e mode (sclk output mode) in sclk input mode, the data is shifted to receiving buffer 1 when th e sclk input becomes active after the receive interrupt flag intes0 is cleared by reading the received data. when 8-bit data is received, the data will be shifted to receiving bu ffer 2 (sc0buf according to the timing shown below) and intes0 will be set again to be generate intrx0 interrupt. figure 8-11 receiving op eration in i/o interfac e mode (sclk input mode) note: the system must be put in the receive enable state (sc0mod0 = 1) before data can be received. bit 0 bit 1 bit 6 bit 7 sclk0 output ( = 0: rising edge mode) sclk0 output ( = 1: falling edge mode) rxd0 irx0c (intrx0 interrupt request) bit 0 bit 1 bit 5 bit 6 bit 7 sclk0 input ( = 1: falling edge mode) sclk0 input ( = 0: rising edge mode) rxd1 irx0c (intrx0 interrupt request)
page 155 2007-10-15 tmp91fw60 8.4.1.3 transmission and receiving (full duplex mode) when the full duplex mode is used, set the level of r eceive interrupt to ?0? and set enable the interrupt level (1 to 6) to the transmission interrupt. in the transmission inte rrupt program, the receiving operation should be done like the above example before setting the next transmission data. example: channel 0, sclk output baud rate = 9600 bps fc = 14.7456 mhz note: x: don't care, ?: no change, *: data *clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: f fph port setting 76543210 intes0 x0010000set the inttx0 level to 1. set the intrx0 level to 0. sc0mod0 ????00??select i/o interface mode. sc0mod1 ? 1xxxxxxselect full duplex m ode. sc0cr ??????00sclk0 output mode, transmit on falling edge mode, receive on rising edge mode. br0cr 00110011b aud rate = 9600 bps sc0mod0 ??1?????e nable receiving sc0buf ********set the transmit data and start. 76543210 acc sc0buf read the receiving buffer. sc0buf ********set the next transmission data.
page 156 2007-10-15 tmp91fw60 8.4.2 mode 1 (7-bit uart mode) 7-bit uart mode is selected by setting serial channel mode register sc0mod0 to ?01?. in this mode, a parity bit can be added. use of a parity bit is enabled or disabled by the setting of the serial channel control register sc0cr bit; whether even parity or odd parity will be used is determined by the sc0cr setting when sc0cr is set to ?1? (enabled). example: when transmission data of the following format, the control registers should be set as described below. this explanation applies to channel 0. figure 8-12 7-bit uart mode note:x: don't care, ?: no change, *: data *clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: system clock 76543210 sc0mod0 ????0101select 7-bit uart mode. sc0cr ? 1 1 ? ? ? ? ? add even parity. br0cr 0 0 1 0 0 1 0 1 set the transmission rate to 2400 bps. intes0 x 1 0 0 ? ? ? ? enable the inttx0 interrupt and set it to interrupt level 4. sc0buf ********set data for transmission. stop start bit 0 1 2 3 4 5 6 even parity transmission direction (transmission rate: 2400 bps at fc = 12.288 mhz)
page 157 2007-10-15 tmp91fw60 8.4.3 mode 2 (8-bit uart mode) 8-bit uart mode is selected by setting sc0mod0 to ?10?. in this mode, a parity bit can be added (use of a parity bit is enabled or disabled by the setting of sc0cr); whether even parity or odd parity will be used is determined by the sc0cr setting when sc0cr is set to ?1? (enabled). example: when receiving data of the following form at, the control registers should be set as described below. figure 8-13 8-bit uart mode note:x: don't care, ?: no change *clock state system clock: high frequency (fc) clock gear: 1 (fc) prescaler clock: system clock 76543210 sc0mod0 ??1?1001e nable receiving in 8-bit uart mode. sc0cr ?01?????add odd parity. br0cr 00010101set the transmission rate to 9600 bps. intes0 ????x100e nable the inttx0 interrupt and set it to interrupt level 4. acc sc0cr and 00011100 if acc 0 then error acc sc0buf check for errors. read the received data. stop start bit 0 1 2 3 4 5 6 7 odd parity transmission direction (transmission rate: 9600 bps at fc = 12.288 mhz)
page 158 2007-10-15 tmp91fw60 8.4.4 mode 3 (9-bit uart mode) 9-bit uart mode is selected by setting sc0mod0 to ?11?. in this mode parity bit cannot be added. in the case of transmission, the msb (9th bit) is wr itten to sc0mod0. in the case of receiving, it is stored in sc0cr. when the buffer is written and read , the msb is read or written first, before the rest of the sc0buf data. 8.4.4.1 wakeup function in 9-bit uart mode, the wakeup function for slave controllers is enabled by setting sc0mod0 to ?1?. the interrupt intrx0 occurs only when = ?1?. note: the txd pin of each slave controll er must be in open-drain output mode. figure 8-14 serial link using wakeup function txd rxd 5ncxg txd rxd 5ncxg txd rxd 5ncxg txd rxd /cuvgt
page 159 2007-10-15 tmp91fw60 8.4.4.2 protocol 1. select 9-bit uart mode on th e master and slave controllers. 2. set the sc0mod0 bit on each slave contro ller to ?1? to enable data receiving. 3. the master controller transmits one-frame data in cluding the 8-bit select code for the slave con- trollers. the msb (bit8) is set to ?1?. 4. each slave controller receives th e above frame. each controller checks the above select code against its own select code. the controller w hose code matches clears its wu bit to ?0?. 5. the master controller transmits data to the specified slave controll er whose sc0mod0 bit is cleared to ?0?. the msb (bit8) is cleared to ?0?. 6. the other slave controllers (who se bits remain at ?1?) ignore the received data because their msbs (bit8 or ) are set to ?0?, disabling intrx0 interrupts. the slave controller (wu bit = ?0?) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master cont roller by this transmission. stop start bit 0 1 2 3 4 5 6 78 "1" select code of slave controller stop start bit 0 1 2 3 4 5 6 7bit 8 &cvc "0"
page 160 2007-10-15 tmp91fw60 8.4.4.3 example to link two slave controllers seri ally with the master controll er using the internal clock f sys as the transfer clock. main settings (exce pt port setting) register msb lsb 76543210 intes0 x100x101 enable the inttx0 interrupt and set it to interrupt level 4. enable the intrx0 interrupt and set it to interrupt level 5. sc0mod0 10101110 set f sys as the transmission clock for 9-bit uart mode. sc0buf 00000001set the select code for slave controller 1. inttx0 interrupt register msb lsb 76543210 sc0mod0 0???????set tb8 to ?0?. sc0buf ********set data for transmission. main settings (except port setting) register msb lsb 76543210 intes0 x 1 0 1 x 1 1 0 enable intrx0 and inttx0. sc0mod0 00111110 set to ?1? in 9-bit uart transmission mode using f sys as the transmission clock. intrx0 interrupt register msb lsb 76543210 acc sc0buf, if acc = select code then sc0mod0 ???0????clear to ?0?. txd rxd 5ncxg txd rxd 5ncxg txd rxd /cuvgt 5gngeveqfg 00000001 5gngeveqfg 00001010
page 161 2007-10-15 tmp91fw60 9. serial bus interface (sbi) the tmp91fw60 has a 2-channel serial bus interface which an i 2 c bus mode. this circuit supports only i 2 c bus mode (multi master). the serial bus interface is connected to an extern al device through sda0,scl0,sda1 and scl1 in the i 2 c bus mode. 9.1 configuration figure 9-1 serial bus interface (sbi) 9.2 serial bus int erface (sbi) control the following registers are used to control the serial bus interface and monitor the op eration status. ? serial bus interface control register 0 (sbi0cr0, sbi1cr0) ? serial bus interface control register 1 (sbi0cr1, sbi1cr1) ? serial bus interface control register 2 (sbi0cr2, sbi1cr2) ? serial bus interface data buffe r register (sbi0dbr, sbi1dbr) ?i 2 c bus address register (i2c0ar, i2c1ar) ? serial bus interface status register (sbi0sr, sbi1sr) ? idle2 control register (sbi0br, sbi1br) 0qkug ecpegnngt scl +prwv output control sda sdan scln   5jkhv tgikuvgt i 2 c bus fcvc eqpvtqn hu[u 0qvgp sbinbr sbin control register 2/ sbin status register sbin control  register 1 sbin baud rate registers i 2 c bus/ address register sbin data/ buffer register sbincr1 i2cnar sbincr2/ sbinsr sbindbr intsbi interrupt request transfer control  circuit noise canceller i 2 c bus clock sysn. control divider
page 162 2007-10-15 tmp91fw60 9.3 operation in i 2 c bus mode both channels operate in the same function except for th e following points; hence only the operation of channel 0 is explained below. 9.3.1 the data formats in the i 2 c bus mode the data formats in the i 2 c bus mode is shown below. figure 9-2 data format in the i 2 c bus mode 8 bits 1 1 or more 1 to 8 bits 1 1 s a c k a c k a c k p slave address data data 1 to 8 bits 1 r / w 8 bits 1 1 1 or more 1 or more 1 to 8 bits 1 1 1 s a c k a c k a c k p slave address data data slave address 1 to 8 bits 1 r / w 8 bits a c k r / w 8 bits 1 1 or more 1 to 8 bits 1 1 s a c k a c k a c k p s data data data 1 to 8 bits 1 (a) addressing format (b) addressing format (with restart) (c) free data format (data transferred from master device to slave device) s r/w ack p : start condition : direction bit : acknowledge bit : stop condition
page 163 2007-10-15 tmp91fw60 9.3.2 i 2 c bus mode control register the following registers are used to control and monitor the operation stat us when using the serial bus inter- face (sbi) in the i 2 c bus mode. serial bus interface control register 0 (read-modify-write instructions are prohibited.) 76543210 sbi0cr0 (0247h) bit symbol sbi0en??????? read/write r/w r after reset00000000 sbi1cr0 (024fh) bit symbol sbi1en??????? read/write r/w r after reset00000000 function sbi operation 0: disable 1: enable always read "0". note : when using sbi, shoul d be set "1" (sbi operation enable) before se tting each register of sbi module. serial bus interface control register 1 (read-modify-write instructions are prohibited.) 76543210 sbi0cr1 (0240h) bit symbol bc2 bc1 bc0 ack ? sck2 sck1 sck0/ swrmon read/write w r/w ? w r/w after reset0000?000/1 sbi1cr1 (0248h) bit symbol bc2 bc1 bc0 ack ? sck2 sck1 sck0/ swrmon read/write w r/w ? w r/w after reset0000?000/1 function number of transferred bits (note 1) acknowl- edge mode specification internal serial clock selection and software reset monitor (note 2) internal serial clock selection at write sck2:0 000 n = 4 ? (note3) system clock : fc clock gear: fc/1 fc =20 mhz (internal scl output) fscl = (f sys /2) / (2 n +36) [hz] 001 n = 5 73.53 khz 010 n = 6 50.00 khz 011 n = 7 30.49 khz 100 n = 8 17.12 khz 101 n = 9 9.12 khz 110 n = 10 4.72 khz 111 (reserved) (reserved) software reset state monitor at read swrmon 0 during software reset 1 initial data acknowledge mode specification ack 0 not generate clock pulse for acknowledge signal 1 generate clock pulse for acknowledge signal
page 164 2007-10-15 tmp91fw60 note 1: for the frequency of the scl line clock, see 9.3.3.3 ?serial clock?. note 2: initial data of sck0 is ?0?,swrmon is ?1?. note 3: this i 2 c bus circuit dose not support high-s peed mode, it supports standard mode only. the fscl speed can be selected over 100 kbps by fc and , however it?s irregular operation. number of bits transferred bc2:0 = 0 = 1 number of clock pulses bits number of clock pulses bits 0008898 0011121 0102232 0113343 1004454 1015565 1106676 1117787
page 165 2007-10-15 tmp91fw60 note 1: reading this register functions as sbi0sr/sbi1sr register. note 2: switch to port mode after confirming that the bus is free. switch a mode between i 2 c bus mode and clocked-synchronous 8-bit sio mode after confirming that input signals via port are high level. serial bus interface control register 2 (read-modify-write instructions are prohibited.) 76543210 sbi0cr2 (0243h) bit symbol mst trx bb pin sbim1 sbim0 swrst1 swrst0 read/write w w w after reset00010000 sbi1cr2 (024bh) bit symbol mst trx bb pin sbim1 sbim0 swrst1 swrst0 read/write w w w after reset00010000 function master/slave selection transmitter/ receiver selection start/stop condition generation cancel intsbi interrupt request serial bus interface opera- tion mode selection software reset generate software reset generate swrst1:0 10 01 write ?10? and ?01?, then an internal reset signal is generated serial bus interface operating mode selection (note 2) sbim1:0 00 port mode (serial bus interface output disabled) 01 (reserved) 10 i 2 c bus mode 11 (reserved) intsbi interrupt request pin 0? 1 cancel interrupt request start/stop condition generation bb 0 generates the stop condition 1 generates the start condition transmitter/receiver selection trx 0 receiver 1 transmitter master/slave selection mst 0slave 1master
page 166 2007-10-15 tmp91fw60 note 1: writing in this register functions as sbi0cr2/sbi1cr2. note 2: the initial data sbi0sr/sbi1sr is "1" if sbi operation is enable (sbi0cr0/sbi1cr0 "1"). if sbi operation is disable (sbi0cr0/sbi1cr0 "0"), the initial data of sbi0sr/sbi1sr is "0". serial bus interface status register (read-modify-write instructions are prohibited.) 76543210 sbi0sr (0243h) bit symbol mst trx bb pin al aas ad0 lrb read/write r after reset00010000 sbi1sr (024bh) bit symbol mst trx bb pin al aas ad0 lrb read/write r after reset00010000 function master/slave status moni- tor transmitter/ receiver sta- tus monitor i 2 c bus sta- tus monitor intsbi interrupt request monitor arbitration lost detection monitor slave address match detec- tion monitor general call detec- tion monitor last received bit monitor last received bit monitor lrb 0 last received bit was 0 1 last received bit was 1 general call detection monitor ad0 0 undetected 1 general call detected slave address match detection monitor aas 0 undetected 1 slave address match or general call detected arbitration lost detection monitor al 0? 1 arbitration lost detected intsbi interrupt request monitor pin 0 interrupt requested 1 interrupt canceled i 2 c bus status monitor bb 0free 1busy transmitter/receiver status monitor trx 0 receiver 1 transmitter master/slave status monitor mst 0slave 1master
page 167 2007-10-15 tmp91fw60 note 1: when writing transmitted data, start from the msb (bit7).receiving data is placed from lsb (bit0). note 2: sbi0dbr can?t be read the written data. therefore read-m odify-write instruction (e.g., ?bit? instruction) is prohibitted . idle2 control register (read-modify-write instru ctions are prohibited.) 76543210 sbi0br (0244h) bit symbol ? i2sbi0 ? ? ? ? ? ? read/write w r/w ? ? ? ? ? r/w after reset00?????0 sbi1br (024ch) bit symbol ? i2sbi1 ? ? ? ? ? ? read/write w r/w ? ? ? ? ? r/w after reset00?????0 function always write ?0? operation in idle2 mode 0: stop 1: operate always write ?0? serial bus interface data buffer register (read-modify-write instru ctions are prohibited.) 76543210 sbi0dbr (0241h) bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (received)/w (transfer) after reset undefined sbi1dbr (0249h) bit symbol db7 db6 db5 db4 db3 db2 db1 db0 read/write r (received)/w (transfer) after reset undefined i 2 c bus address register (read-modify-write instructions are prohibited.) 76543210 i2c0ar (0242h) bit symbol sa6 sa5 sa4 sa3 sa2 sa1 sa0 als read/write w after reset00000000 i2c1ar (024ah) bit symbol sa6 sa5 sa4 sa3 sa2 sa1 sa0 als read/write w after reset00000000 function slave address selection for wh en device is operatin g as slave device address recognition mode speci- fication address recognition mode specification als 0 slave address recognition 1 non slave address recognition
page 168 2007-10-15 tmp91fw60 9.3.3 control in i 2 c bus mode 9.3.3.1 acknowledge mode specification set the sbi0cr1 to ? 1 ? for operation in the acknowledge mode. the tmp91fw60 generates an additional clock pulse for an acknowledge signal when operating in master mode. in the transmitter mode during the clock pulse cycle, the sda pin is released in order to receive the acknowledge signal from the receiver. in the receiver mode during the clock pulse cycle, the sda pin is set to the low in order to gener- ate the acknowledge signal. clear the to ? 0 ? for operation in the non-acknowledge mode, the tmp91fw60 does not gener- ate a clock pulse for the acknowledge signal when operating in the master mode. 9.3.3.2 number of transfer bits the sbi0cr1 is used to se lect a number of bits for next transmitting and receiving data. since the is cleared to ? 000 ? as a start condition, a slave addr ess and direction bit transmission are always executed in 8 bits. other than th ese, the retains a specified value. 9.3.3.3 serial clock (1) clock source the sbi0cr1 is used to select a maximum transfer frequency outputted on the scl pin in master mode. set the baud rates, which have been calculated according to the formula below, to meet the specifications of the i2c bus, such as the smallest pulse width of tlow. figure 9-3 clock source note: f sbi shows f sys /2 t low = (2 n ? 1 +29)/f sbi t high = (2 n ? 1 +7)/f sbi fscl = 1/(t low + t high ) = f sbi /(2 n + 36) sbi0cr1 n 000 001 010 011 100 101 110 4 5 6 7 8 9 10 1/fscl t low t high
page 169 2007-10-15 tmp91fw60 (2) clock synchronization in the i 2 c bus mode, in order to wired-and a bus, a master device which pulls down a clock line to low level, in the first place, invalidate a cloc k pulse of another master device which generates a high-level clock pulse. the master device with a high-level clock pulse needs to detect the situation and implement the fo llowing procedure. the tmp91fw60 has a clock synchronization functi on for normal data transfer even when more than one master exists on the bus. the example explains the clock synchronization procedures wh en two masters simultaneously exist on a bus. figure 9-4 clo ck synchronization as master a pulls down the internal scl output to the low level at point ?a?, the scl line of the bus becomes the low level. after detecting this s ituation, master b resets a counter of high-level width of an own clock pulse and sets the internal scl output to the low level. master a finishes counting low-level width of an own clock pulse at point ?b? and sets the internal scl output to the high level. since master b holds th e scl line of the bus at the low level, master a waits for counting high-level width of an own cloc k pulse. after master b finishes counting low- level width of an own clock pulse at point ?c? and master a detects the scl line of the bus at the high level, and starts counting high level of an ow n clock pulse. the clock pulse on the bus is deter- mined by the master device with the shortest high-l evel width and the master device with the longest low-level width from among those master devices connected to the bus. 9.3.3.4 slave address and address recognition mode specification when the tmp91fw60 is used as a slave device, set the slave address and to the i2c0ar. clear the to ?0? for the address recognition mode. 9.3.3.5 master/slave selection set the sbi0cr2 to ?1? for operating the tmp91fw60 as a master device. clear the sbi0cr2 to ?0? for operation as a slave devi ce. the is cleared to ?0? by the hardware after a stop condition on the bus is detected or arbitration is lost. abc internal scl output (master a) internal scl output (master b) scl pin start counting high-level width of a clock pulse reset a counter of high-level width of a clock pulse wait counting high-level width of a clock pulse
page 170 2007-10-15 tmp91fw60 9.3.3.6 transmitter/receiver selection set the sbi0cr2 to ?1? for operating the tmp91fw60 as a tr ansmitter. clear the to ?0? for operation as a receiver. when data with an addressing form at is transferred in slave mode, when a slave address with the same value that an i2c0ar or a general call is received (all 8-bit data ar e ?0? after a start condition), the is set to ?1? by the hardware if the direction bit (r/ w ) sent from the master device is ?1?, and is cleared to ?0? by the ha rdware if direction bit is ?0?. in the master mode, after an ac knowledge signal is returned fr om the slave device, the is cleared to ?0? by the hardware if a transmitted directio n bit is ?1?, and is set to ?1? by the hard- ware if direction is ?0?. when an acknowledge signal is not returned, the current condition is maintained. the is cleared to ?0? by the hard ware after a stop condition on the i 2 c bus is detected or arbitra- tion is lost. 9.3.3.7 start/stop condition generation when the sbi0sr is ?0?, slave address and di rection bit which are set to sbi0dbr are output on a bus after generating a start cond ition by writing ?1? to the sbi0cr2. it is neces- sary to set transmitted data to the data buffer register (sbi0dbr) and set ?1? to beforehand. figure 9-5 start condition generat ion and slave address generation when the is ?1?, a sequence of generating a stop condition is started on the bus by writing ?1? to the , and ?0? to the . do not mo dify the contents of until a stop condition is generated on the bus. figure 9-6 stop condition generation the state of the bus can be ascer tained by reading the contents of sbi0sr. sbi0sr will be set to ?1? if a start condition has been detected on th e bus, and will be cleared to ?0? if a stop condition has been detected. a6 a5 2 3 4 5 6 7 8 9 a4 a3 a2 a1 a0 r/ w 1 slave address and the direction bit scl pin sda pin start condition acknowledge signal scl pin sda pin stop condition
page 171 2007-10-15 tmp91fw60 9.3.3.8 interrupt service requests and interrupt cancellation when a serial bus interface interr upt request (intsbi) occurs, the sbi0cr2 is cleared to ?0?. during the time that the sbi0cr2 is ?0?, the scl line is pulled down to the low level. the is cleared to ?0? when an 1 word of da ta is transmitted or receive d. either writing/reading data to/from sbi0dbr sets the to ?1?. the time from the being set to ?1? until the scl line is released takes t low . in the address recognition mode ( = ?0?),

is cleared to ?0? when the received slave address is the same as the value set at the i2c0ar or when a general call is received (all 8-bit data are ?0? after a start condi tion). although sbi0cr2 can be set to ?1? by the program, the is not cleared to ?0? when it is written ?0?. 9.3.3.9 serial bus interface operation mode selection sbi0cr2 is used to specify the serial bus interface operation mode. set sbi0cr2 to ?10? when the device is to be used in i 2 c bus mode after confirming pin condition of serial bus interface to ?h?. switch to port mode after confirming a bus is free. 9.3.3.10 arbitration lost detection monitor since more than one master device can exist simultaneously on the bus in i 2 c bus mode, a bus arbitra- tion procedure has been implem ented in order to guarantee the integrity of transferred data. data on the sda line is used for i 2 c bus arbitration. the following shows an example of a bus arbitration procedure when two master devices exist simulta- neously on the bus. master a and master b output th e same data until point ?a?. after master a outputs ?l? and master b, ?h?, the sda line of the bus is wired-and and the sda line is pulled down to the low level by master a. when the scl line of the bus is pul led up at point b, the slave device reads the data on the sda line, that is, data in master a. a data tr ansmitted from master b becomes invalid. the state in master b is called ?arbitration lost?. master b device which loses arbitra tion releases the internal sda output in order not to affect data transmitted from other masters with arbitration. when more than one master sends the same data at the first word, arbitration occurs continuou sly after the second word. figure 9-7 arbitration lost the tmp91fw60 compares the levels on the bus?s sda line with those of the internal sda output on the rising edge of the scl line. if the levels do not match, arbitration is lost and sbi0sr is set to ?1?. ab scl pin internal sda output (master a) internal sda output (master b) sda pin internal sda output becomes 1 after arbitration has been lost.
page 172 2007-10-15 tmp91fw60 when sbi0sr is set to ?1?, sbi0sr are cleared to ?00? and the mode is switched to slave receiver mode. thus, clock output is sto pped in data transfer after setting = ?1?. sbi0sr is cleared to ?0 ? when data is written to or read from sbi0dbr or when data is written to sbi0cr2. figure 9-8 example of when tmp91fw60 is a master de vice b (d7a = d7b, d6a = d6b) 9.3.3.11 slave address match detection monitor sbi0sr is set to ?1? in sl ave mode, in address recognition mode (e.g., when i2c0ar = ?0?), when a general call is recei ved, or when a slave address matches the value set in i2c0ar. when i2c0ar = ?1?, sbi0sr is set to ?1? after the first word of data has been received. sbi0sr is cleared to ?0? when data is written to or read from the data buffer register sbi0dbr. 9.3.3.12 general call detection monitor sbi0sr is set to ?1? in slave mode, when a general call is r eceived (all 8-bit received data is ?0? after a start condition). sbi0sr is cleared to ?0? when a start condition or stop condi- tion is detected on the bus. 9.3.3.13 last received bit monitor the sda line value stored at the rising edge of the scl line is set to the sbi0sr. in the acknowledge mode, immediately after an intsbi interrup t request is generated, an acknowledge signal is read by reading the conten ts of the sbi0sr. 9.3.3.14 software reset function the software reset function is used to initialize th e sbi circuit, when sbi is locked by external noises, etc. an internal reset signal pulse can be generated by setting sbi0cr2 to ?10? and ?01?. this initializes the sbi circuit internally. all control registers and status registers are initialized as well. sbi0cr1 is automatically set to ?1? after the sbi circuit has been initialized. note: if the software reset is executed, operation selection is reset, and its mode is set to port mode from i 2 c mode. d7a d6a d5a d4a d7b d6b d3a d2a d1a d6a' d7a' d5a' d4a' d0a 1 2 3 4 1 2 3 4 5 6 7 8 9 1 2 3 4 internal scl output accessed to sbi0dbr or sbi0cr2 internal sda output internal scl output internal sda output master a master b stop the clock pulse keep internal sda output to high level as losing arbitration
page 173 2007-10-15 tmp91fw60 9.3.3.15 serial bus interface data buffer register (sbi0dbr) the received data can be read and transferred data can be written by readi ng or writing the sbi0dbr. in the master mode, after the start condition is generated the slave address and the direction bit are set in this register. 9.3.3.16 i 2 cbus address register (i2c0ar) i2c0ar is used to set the slave address when the tmp91fw60 functions as a slave device. the slave address output from the master device is recognized by setting the i2c0ar to ?0?. the data format is the addressing format. when the slave address is not recognized at the = ?1?, the data format is the free data format. 9.3.3.17 setting register for idle2 mode operation (sbi0br0) sbi0br0 is the register setting operat ion/stop during idle2 mode. therefore, setting is necessary before th e halt instruction is executed. 9.3.4 data transfer in i 2 c bus mode 9.3.4.1 device initialization set the sbi0cr1, clear bits 2 to 0 and 4 in the sbi0cr1 to ?0?. set a slave address and th e ( = ?0? when an ad dressing format) to the i2c0ar. for specifying the default setting to a slave receive r mode, clear ?0? to the sbi0cr2, set ?1? to the , ? 10? to the , and write ?0? to bit 1, 0. 76543210 sbi0cr1 x x x 0 x 0 0 0 set acknowledge and scl clock. i2c0ar x x x x x x x 0 set slave address and address recognition mode. sbi0cr2 00011000 set to slave receiver mode. note: x: don?t care
page 174 2007-10-15 tmp91fw60 9.3.4.2 start condition and slave address generation (1) master mode in the master mode, the star t condition and the slave address are generated as follows. check a bus free status (when = ?0?). set the sbi0cr1 to ?1? (acknowledge mode ) and specify a slave address and a direction bit to be transmitted to the sbi0dbr. when sbi0cr2 = ?0?, the start condition are generated by writing ?1? to sbi0cr2. subsequently to the start condition, nine clocks are output from the scl pin. while eight clocks are output, th e slave address and the direction bit wh ich are set to the sbi0dbr. at the 9th clock, the sda line is releas ed and the acknowledge signal is received from the slave device. an intsbi0 interrupt request occurs at the falling edge of the 9th clock. the is cleared to ?0?. in the master mode, the scl pin is pulled dow n to the low level while is ?0?. when an interrupt request occurs, the is changed according to the dir ection bit only when an acknowl- edge signal is returned from the slave device. in intsbi0 interrupt routine intclr <-- 0x30 ; clear the interrupt request process end of interrupt (2) slave mode in the slave mode, the start conditio n and the slave address are received. after the start condition is receive d from the master device, while eight clocks are output from the scl pin, the slave address and the direction bit whic h are output from the mast er device are received. when a general call or the same address as the slave address set in i2c0ar is received, the sda line is pulled down to the low level at the 9th clock, and the acknowledge signal is output. an intsbi0 interrupt request occurs on the falling edge of the 9th clock. the is cleared to ?0?. in slave mode the scl line is pulled down to the low level while the = ?0?. setting in main routine 76543210 reg sbi0sr reg reg. 0x20 if reg 0x00 wait until bus is free. then sbi0cr1 x x x 1 x 0 0 0 set to acknowledgement mode. sbi0dbr x x x x x x x x set slave address and direction bit. sbi0cr2 11111000 generate start condition.
page 175 2007-10-15 tmp91fw60 figure 9-9 start condition gener ation and slave address transfer 9.3.4.3 1-word data transfer check the by the intsbi0 inte rrupt process after the 1-word da ta transfer is completed, and determine whether the mode is a master or slave. (1) if = ?1? (master mode) check the and determine whether th e mode is a transmitter or receiver. (a) when the = ?1? (transmitter mode) check the . when is ?1?, a receive r does not request da ta. implement the pro- cess to generate a stop condition (refer to below) and terminate data transfer. when the is ?0?, the receiver requests ne w data. when the next transmitted data is 8 bits, write the transmitted data to sbi0dbr. wh en the next transmitted data is other than 8 bits, set the and write the transmitted data to sbi0dbr. after written the data, becomes ?1?, a seri al clock pulse is generated for transferring a new 1 word of data from the scl pin, and then the 1-word data is transmitted. after the data is transmitted, an intsbi interrupt request occurs. the becomes ?0? and the scl line is pulled down to the low level. if the data to be transferred is mo re than one word in lengt h, repeat the procedure from the checking above. if mst = 0 then shift to the process when slave mode if trx = 0 then shift to the process when receiver mode. if lrb = 0 then shift to the process that generates stop condition. 76543210 sbi0cr1 0 0 0 1 x x x x set the bit number of transmit and ack. sbi0dbr xxxxxxxx write the transmit data. end of interrupt note: x: don?t care a6 a5 2 3 4 5 6 7 8 9 a4 a3 a2 a1 a0 ack r/w 1 scl pin sda pin intsbi interrupt request start condition slave address + direction bit output of master output of slave acknowledge signal from a slave device
page 176 2007-10-15 tmp91fw60 figure 9-10 example in wh ich = ?000? and = ?1? in transmitter mode (b) when the is ?0? (receiver mode) when the next transmitted data is other than 8 bits, set and read the received data from sbi0dbr to release the scl line (data which is read immediately after a slave address is sent is undefined). after the data is read, becomes ?1?. serial clock pulse for transferring new 1 word of data is defined scl and outputs ?l? level from sda pin with acknowledge timing. an intsbi0 interrupt request then occurs and the becomes ?0?, then the tmp91fw60 pulls down the scl pin to the low level. the tmp91fw60 outputs a clock pulse for 1 word of data tran sfer and the acknowledge signal each ti me that received data is read from the sbi0dbr. figure 9-11 example of when = ?000?, = ?1 ? in receiver mode in order to terminate the transmission of da ta to a transmitter, cl ear to ?0? before reading data which is 1 word before the last da ta to be received. the last data word does not generate a clock pulse as the acknowledge signal. after the data has been transmitted and an interrupt request has been generated, set to ?001? and read the data. the tmp91fw60 generates a clock pulse for an 1-bit data transfer. since the master device is a receiver, the sda line on the bus remains high. the transmitter interprets the high signal as an ack signal. the receiver indicates to the tran smitter that data transfer is complete. after the one data bit has been received a nd an interrupt request been generated, the tmp91fw60 generates a stop condition and terminates data transfer. d7 d6 2 3 4 5 6 7 8 9 d5 d4 d3 d2 d1 d0 ack 1 scl pin write to sbi0dbr sda pin intsbi interrupt request output from master output from slave acknowledge signal from a receiver d7 d6 2 3 4 5 6 7 8 9 d5 d4 d3 d2 d1 ack 4 d7 d0 1 scl pin read sbi0dbr sda pin intsbi interrupt request output from master output from slave acknowledge signal to a
page 177 2007-10-15 tmp91fw60 figure 9-12 termination of data transfer in mast er receiver mode (2) if = 0 (slave mode) in the slave mode the tmp91fw60 operates either in normal slav e mode or in slave mode after losing arbitration. in the slave mode, an intsbi0 interrupt request occurs when the tmp91fw60 receives a slave address or a general call from the master device, or when a general call is received and data transfer is complete, or af ter matching received address. in the master mode, the tmp91fw60 operates in a slave mode if it detects losing arbitr ation. an intsbi0 interrupt request occurs when a word data transfer terminates af ter losing arbitration. when an in tsbi0 interrupt request occurs the is cleared to ?0? and the scl pin is pulled down to the low level. either reading/writing from/ to the sbi0dbr or setting the to ?1 ? will release the scl pin after taking t low time. check the sbi0sr, , , and and implements processes according to conditions listed in the next table. example: in case receive data n times intsbi0 interrupt (after transmitting data) 76543210 sbi0cr1 x x x x x x x x set the bit number of receive data and ack. reg. sbi0dbr load the dummy data. end of interrupt intsbi0 interrupt (receive data of 1st to (n 2) th) 76543210 reg. sbi0dbr load the data of 1st to (n 2)th. end of interrupt intsbi0 interrupt ((n 1) th receive data) 76543210 sbi0cr1 x x x 0 0 x x x not generate acknowledge signal reg. sbi0dbr load the data of (n 1)th end of interrupt intsbi0 interrupt (nth receive data) 76543210 sbi0cr1 0 0 1 0 0 x x x generate the clock for 1bit transmit reg. sbi0dbr receive the data of nth. end of interrupt intsbi0 interrupt (after receiving data) the process of generating stop condition finish the transmit of data end of interrupt note: x: don?t care d7 d6 2 9 3 4 5 6 7 8 1 d5 d4 d2 d3 d1 d0 1 scl pin sda pin intsbi interrupt request "0"  read sbi0dbr "001"  read sbi0dbr output of master output of slave acknowledge si g sent to a transmi t
page 178 2007-10-15 tmp91fw60 example: in case matching slave address in slave receive mode, direction bit is "1". intsbi0 interrupt if trx = 0 then shift to other process if al = 1 then shift to other process if aas = 0 then shift to other process 76543210 sbi0cr1 x x x 1 x x x x set the bit number of transmit. sbi0dbr x x x x x x x x set the data of transmit. note: x: don?t care table 9-1 operation in the slave mode conditions process 1 110 the tmp91fw60 loses arbitration when transmitting a slave address and receives a slave address for which the value of the direction bit sent from another master is ?1?. set the number of bits a word in and write the transmitted data to sbi0dbr. 0 10 in slave receiver mode, the tmp91fw60 receives a slave address for which the value of the direction bit sent from the master is ?1?. 00 in slave transmitter mode, a single word of data is transmitted. check the setting. if is set to ?1?, set to ?1? since the receiver win no request the data which follows. then, clear to ?0? to release the bus. if is cleared to ?0?, set to the number of bits in a word and write the transmitted data to sbi0dbr since the receiver requests next data. 0 1 11/0 the tmp91fw60 loses arbitration when transmitting a slave address and receives a slave address or general call for which the value of the direction bit sent from another master is ?0?. read the sbi0dbr for setting the to ?1? (reading dummy data) or set the to ?1?. 00 the tmp91fw60 loses arbitration when transmitting a slave address or data and terminates word data transfer. 0 11/0 in slave receiver mode, the tmp91fw60 receives a slave address or general call for which the value of the direction bit sent from the master is ?0?. 01/0 in slave receiver mode, the tmp91fw60 terminates receiving word data. set to the number of bits in a word and read the received data from sbi0dbr.
page 179 2007-10-15 tmp91fw60 9.3.4.4 stop condition generation when sbi0sr = ?1?, the sequence for generating a stop condition is started by writing ?1? to sbi0cr2 and ?0? to sbi0cr2. do not modify the contents of sbi0cr2 until a stop condition has been generated on the bus. when the bus?s scl line has been pulled low by another device, the tmp91fw60 gene rates a stop condition when the other device has released the scl line and sda pin rising. figure 9-13 stop condition generation (single master) figure 9-14 condition g eneration (multi master) 76543210 sbi0cr2 1 1 0 1 1 0 0 0 generate stop condition. internal scl 1  "1"  "0"  "1"  sda pin (read) stop condition scl pin internal scl "1"  "1"  "0"  "1"  sda pin (read) stop condition the case of pulled low by another device
page 180 2007-10-15 tmp91fw60 9.3.4.5 restart restart is used during data transfer between a mast er device and a slave to change the data transfer direction. the following description explains how to rest art when the tmp91fw60 is in master mode. clear sbi0cr2 to ?0? and set sbi0 cr2 to ?1? to release the bus. the sda line remains high and the scl pin is released. since a stop condition has not been generated on the bus, other devices assume the bus to be in busy state. and confirm scl pin, that scl pin is released and become bus-free state by sbi0sr = ?0? or signal level ?1? of scl pin by sensing its port (chang e to input mode). check the until it becomes ?1? to check that the scl line on a bus is not pulled down to the low level by other devices. after con- firming that the bus remains in a free state, genera te a start condition using the procedure described in 9.3.4.2. in order to satisfy the setup time requirem ents when restarting, take at least 4.7 s of waiting time by software from the time of restarting to confirm that th e bus is free until the time to generate the start con- dition. figure 9-15 timing diagr am for tmp91fw60 restart note: don't write "0", when "0" condition. (cannot be restarted) 76543210 sbi0cr2 00011000 release the bus if sbi0sr 0 check if scl pin is released. then if sbi0sr 1 check if scl pin of other device is "l" level. then 4.7us wait sbi0cr1 0 0 0 1 0 x x x set acknowledgement mode. sbi0dbr x x x x x x x x set the slave address and direction bit. sbi0cr2 11111000 generate start condition. note: x: don?t care "0"  "0"  "0"  "1"  "1"  "1"  "1"  "1"  9 internal scl scl pin sda pin start condition 4.7 s (min)
page 181 2007-10-15 tmp91fw60 10. 10-bit ad converter (adc) the tmp91fw60 have a 10-bit successive approximation ty pe ad converter. 10.1 configuration the circuit configuration of the 10-bit ad converter is shown in figure 10-1 . it consists of control register adccr1 and adccr2, converted value register adcdrh and adcdrl, a da converter, a sample-hold circuit, a compar ator, and a successive comparison circuit. note: before using ad converter, set appropriate value to i/o port register combining a analog input port. for details, see the sec- tion on "i/o ports". figure 10-1 10-bit ad converter 10.2 register configuration the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels and operation mode (single or repeat) in which to perform ad conversion and controls the ad converter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and co ntrols the connection of the da converter (ladder resistor network) and monitors the operating status of the ad converter. 3. ad converted value register (adcdrh, adcdrl) this register used to store the digital value after being converted by the ad converter. #0 #0   #0 #0 #%-  5#+0 #+0'0 #& 4 5    8 4'(*  # 855       # $      1 2 ; '0    5   #&%%4  # 8%%  4 4 4   #/&  #&%%4 #&%&4.  #&%&4*   ' 1 % ( # & $ ( +06#&      45'.  analog input multiplexer da converter sample hold circuit reference voltage analog comparator shift clock control circuit ad conversion result register 1, 2 ad converter control register 1, 2 successive approximate circuit 5gngevqt
page 182 2007-10-15 tmp91fw60 note 1: select analog input channel during ad converter stops (adccr2 = ?0?). note 2: when the analog input channel is all use dis abling, the adccr1 should be set to ?0?. note 3: during conversion, do not perform port output instruction to maintain a precision for all of the pins because analog inp ut port use as general input port. and for port near to anal og input, do not input intense signaling of change. note 4: the adccr1 is automatically cleared to ?0? after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: starting of stop mode, slow mode, and the idle1 mode initializes the ad control register 1 (adccr1) except for sain. moreover, in the case of the idle2 mode, it controls by the bit of adccr2. therefore, to use ad converter again, set the adccr1 newly after returning to normal mode. note 1: starting of stop mode, slow mode, and the idle1 mode in itializes the ad control register 2 (adccr2) except for ack and i2ad. moreover, in the case of the idle2 mode, it controls by the bit of adccr2. therefore, to use ad con- verter again, set the adccr2 newly after returning to norm al mode. therefore, the ad conversion result should be read to adcdrl more first than adcdrh. note 2: the adccr2 is cleared to ?0? when reading the adcdrh. note 3: the adccr2 is set to ?1? when ad conversi on starts, and cleared to ?0? when ad conversion finished. ad converter control register 1 76543210 adccr1 (02b0h) bit symbol adrs amd ainen sain read/write r/w after reset00000000 function ad conver- sion start 0: - 1: ad con- version start ad operating mode 00: ad operation disable 01: single mode 10: reserved 11: repeat mode analog input control 0:disable 1:enable analog input channel select 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: an9 1010: an10 1011: an11 1100: an12 1101: an13 1110: an14 1111: an15 ad converter control register 2 ( read-modify-write instructions are prohibited.) 76543210 adccr2 (02b1h) bit symbol eocf adbf rsel i2ad ack read/write r r/w after reset00001100 function ad conver- sion end flag 0:before or during con- version 1: conver- sion com- pleted ad conver- sion busy flag 0: during stop of ad conversion 1: during ad conversion storing of an ad conver- sion result 0: 10bit mode 1: 8bit mode idle2 con- trol 0:stop 1:operation ad conversion time select see" table 10-1 ack setting and conversion time "
page 183 2007-10-15 tmp91fw60 note 1: setting for ?-? in the above table are inhibite d. fc: high fr equency oscillation clock [hz] note 2: set conversion time setting should be kept mo re than the following time by analog reference voltage. note: at the time of 10-bit storing mode, if the bit 7 to 2 of adcdrh is read, ?0? will be read. table 10-1 ack setting and conversion time condition conversion time 20mhz 16mhz 10 mhz 8mhz 4 mhz 2 mhz ack 0xxx reserved 1000 reserved 1001 reserved 1010 78/fc ???? 19.5 s 39.0 s 1011 156/fc ?? 15.6 s 19.5 s 39.0 s 78.0 s 1100 312/fc 15.6 s 19.5 s 31.2 s 39.0 s 78.0 s156.0 s 1101 624/fc 31.2 s 39.0 s 62.4 s 78.0 s 156.0 s ? 1110 1248/fc 62.4 s 78.0 s 124.8 s 156.0 s ?? 1111 reserved ? v refh = 4.5 to 5.5 v 15.6 us and more ad converted value register h (8-bit storing mode) 76543210 adcdrh (02b3h) bit symbol ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 read/write r after reset00000000 ad converted value register h (10-bit storing mode) 76543210 adcdrh (02b3h) bit symbol ?????? ad09 ad08 read/write r after reset00000000 ad converted value register l 76543210 adcdrl (02b2h) bit symbol ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 read/write r after reset00000000
page 184 2007-10-15 tmp91fw60 10.3 function 10.3.1 single mode after setting adccr1 to ?01? (single mode), set adccr1 to ?1?. ad conversion of the voltage at the analog input pin specifi ed by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdrh, adcdrl) and at the same time adccr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. adccr1 is automatically cleared after ad c onversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adccr1 newly again, check adccr2 to see that the convers ion is completed or wait until th e interrupt signal (intadc) is gen- erated (e.g., interrupt handling routine). figure 10-2 single mode #&%&4zuvcvwu #&%%4'1%( +06#&%kpvgttwrvtgswguv #&%%4#&$( #&%%4#&45 #&%&4* #&%&4. conversion result read conversion result read conversion result read conversion result read indeterminate 1st conversion result 2nd conversion result ad conversion start ad conversion start eocf cleared by reading conversion result
page 185 2007-10-15 tmp91fw60 10.3.2 repeat mode ad conversion of the voltage at the analog input pin specified by adccr1 is performed repeat- edly. in this mode, ad conversion is star ted by setting adccr1 to ?1? after setting adccr1 to ?11? (repeat mode). after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdrl, adcdrh) and at the same time adccr2 is set to 1, the ad conversion finished inter- rupt (intadc) is generated. in repeat mode, each time one ad conversion is complete d, the next ad conversion is started. to stop ad conversion, set adccr1 to ?00? (disable mode) by writing 0s. the ad convert operation is stopped immediately. the converted valu e at this time is not stored in the ad converted value register. figure 10-3 repeat mode 10.3.3 regi ster setting 1. set up the ad converter control re gister 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). ? specify amd for the ad converter control operation mode (ssingle or repeat mode). 2. set up the ad converter control re gister 2 (adccr2) as follows: set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to table 10-1 and ad converter control register 2. 3. after setting up (1) and (2) above, set ad conversion st art (adrs) of ad converter control register 1 (adccr1) to ?1?. if software start mode has been selected, ad conversi on starts immediately. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register (adcdrh and adcdrl) and the ad conversion finished flag (eocf) of ad converter control register 2 (adccr2) is set to ?1?, upon which time ad conversion interrupt intadc is generated. 5. eocf is cleared to ?0? by a read of the conversion re sult. however, if reconv erted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed.  #/&  '1%(   #&45   +06#&     #&%&4z        #/&  conversion operation ad conversion start 1st conversion result 2nd conversion result 3rd conversion result indeterminate 1st conversion result 3rd conversion result conversion result read ad convert operation suspended. conversion result is not stored. when not performing conversion result read-out, eocf is not cleared and a conversion result is not stored.
page 186 2007-10-15 tmp91fw60 10.4 idle1/stop/slow mo des during ad conversion when standby mode (idle1,stop or slow mode) is entered forcibly during ad conversion, the ad convert operation is suspended and the ad converter is initialized (adccr1 and adccr2 are initia lized to initial value). also, the conversion result is indeterminate. (conversion re sults up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode (idle1,stop or slow mode).) when restored from standby mode (idle1,stop or slow m ode), ad conversion is not automatical ly restarted, so it is necessary to restart ad conversion. note that since the analog reference voltage is automati cally disconnected, there is no possi- bility of current flowing into the analog reference voltage. moreover, in the case of the idle2 mode, it controls by the bit of adccr2. example :after selecting the conversion time 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad con- version once. after checking eocf, read the converted value, store the lower 2 bits in address 0009eh nd store the upper 8 bits in address 0009fh in ram. the operation mode is single mode. ld (adccr1) , 00110011b ; select ain3 ld (adccr2) , 00001100b ;select conversion time(312/fc) and operation mode set (adccr1) . 7 ; adrs = 1(ad conversion start) sloop : test (adccr2) . 7 ; eocf= 1 ? jrs t, sloop ld a , (adcdrl) ; read result data ld (9eh) , a ld a , (adcdrh) ; read result data ld (9fh), a
page 187 2007-10-15 tmp91fw60 10.5 analog input voltage and ad conversion result the analog input voltage is corresponded to the 10-bit digital value converted by the ad as shown in figure 10-4 . figure 10-4 analog i nput voltage and ad c onversion result (typ.) 1 0 01 h 02 h 03 h 3fd h 3fe h 3ff h 2 3 1021 1022 1023 1024 1024 ? 9 8 4'(* # 85 5 analog input voltage a d conversion result
page 188 2007-10-15 tmp91fw60 10.6 precautions about ad converter 10.6.1 analog input pin voltage range make sure the analog input pins (an0 to an15) are used at voltages within v refh to a vss . if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 10.6.2 analog input shared pins the analog input pins (an0 to an15) are shared with input/output ports. when using any of the analog inputs to execute ad convers ion, do not execute in put/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 10.6.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 10-5 . the higher the output imped- ance of the analog input source, more easily they are su sceptible to noise. therefor e, make sure the output impedance of the signal source in your design is 5k or less. toshiba also reco mmends attaching a capacitor external to the chip. figure 10-5 analog i nput equivalent circuit and exam ple of input pin processing  ani 4m
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page 189 2007-10-15 tmp91fw60 11. program patch logic the tmp91fw60 has a program patch logic, which enables the user to fix the program code in the on-chip rom without generating a new mask. patch program must be re ad into on-chip ram from external memory during the startup routine. up to six two-byte sequences, or banks (twelve bytes in total) can be replaced with patch code. more significant code correction can be performed by replacing program code with single-byte instruction code which generates a software interrupt (swi) to make a branch to a specified location in the on-chip ram area. the program patch logic only compares addresses in the on-chip rom area; it cannot fix the program code in the on-chip peripheral, on-chip ram and external rom areas. each of six banks is independently programmable, and f unctionally equivalent. in the following sections, any ref- erences to bank0 also apply to other banks. 11.1 block diagram figure 11-1 progr am patch logic diagram %27 #fftguudwu
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page 190 2007-10-15 tmp91fw60 11.2 sfr descriptions the program patch logic consists of six banks (0 to 5). e ach bank is provided with th ree bytes of address compare registers (romcmpx0 to romcmpx2) and two bytes of address substitution regi sters (romsubxl and rom- subxh). note 1: the romcmp00/01/02, and romsub0l/0h regist ers do not support read-modify-write operation. note 2: bit0 of the address compare register 0 is read as undefined. bank0 address compare register 0 76543210 romcmp00 (0400h) rmw instructions are prohib- ited. bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? read/write w ? after reset0000000 ? function target rom address (lower 7 bits) ? bank0 address compare register 1 76543210 romcmp01 (0401h) rmw instructions are prohib- ited. bit symbol romc15 romc14 romc13 ro mc12 romc11 romc10 romc09 romc08 read/write w after reset00000000 function target rom address (middle 8 bits) bank0 address compare register 2 76543210 romcmp02 (0402h) rmw instructions are prohib- ited. bit symbol romc23 romc22 romc21 ro mc20 romc19 romc18 romc17 romc16 read/write w after reset00000000 function target rom address (upper 8 bits) bank0 data substitution register l 76543210 romsub0l (0404h) rmw instructions are prohib- ited. bit symbol roms07 roms06 roms05 ro ms04 roms03 roms02 roms01 roms00 read/write w after reset00000000 function patch code (lower 8 bits) bank0 data substitution register h 76543210 romsub0h (0405h) rmw instructions are prohib- ited. bit symbol roms15 roms14 roms13 ro ms12 roms11 roms10 roms09 roms08 read/write w after reset00000000 function patch code (upper 8 bits)
page 191 2007-10-15 tmp91fw60 note 1: the romcmp10/11/12, and romsub1l/1h registers do not support read-modify-write operation. note 2: bit0 of the address compare register 0 is read as undefined. bank1 address compare register 0 76543210 romcmp10 (0408h) rmw instructions are prohib- ited. bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? read/write w ? after reset0000000 ? function target rom address (lower 7 bits) ? bank1 address compare register 1 76543210 romcmp11 (0409h) rmw instructions are prohib- ited. bit symbol romc15 romc14 romc13 ro mc12 romc11 romc10 romc09 romc08 read/write w after reset00000000 function target rom address (middle 8 bits) bank1 address compare register 2 76543210 romcmp12 (040ah) rmw instructions are prohib- ited. bit symbol romc23 romc22 romc21 ro mc20 romc19 romc18 romc17 romc16 read/write w after reset00000000 function target rom address (upper 8 bits) bank1 data substitution register l 76543210 romsub1l (040ch) rmw instructions are prohib- ited. bit symbol roms07 roms06 roms05 ro ms04 roms03 roms02 roms01 roms00 read/write w after reset00000000 function patch code (lower 8 bits) bank1 data substitution register h 76543210 romsub1h (040dh) rmw instructions are prohib- ited. bit symbol roms15 roms14 roms13 ro ms12 roms11 roms10 roms09 roms08 read/write w after reset00000000 function patch code (upper 8 bits)
page 192 2007-10-15 tmp91fw60 note 1: the romcmp20/21/22, and romsub2l/2h regist ers do not support read-modify-write operation. note 2: bit0 of the address compare register 0 is read as undefined. bank2 address compare register 0 76543210 romcmp20 (0410h) rmw instructions are prohib- ited. bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? read/write w ? after reset0000000 ? function target rom address (lower 7 bits) ? bank2 address compare register 1 76543210 romcmp21 (0411h) rmw instructions are prohib- ited. bit symbol romc15 romc14 romc13 ro mc12 romc11 romc10 romc09 romc08 read/write w after reset00000000 function target rom address (middle 8 bits) bank2 address compare register 2 76543210 romcmp22 (0412h) rmw instructions are prohib- ited. bit symbol romc23 romc22 romc21 ro mc20 romc19 romc18 romc17 romc16 read/write w after reset00000000 function target rom address (upper 8 bits) bank2 data substitution register l 76543210 romsub2l (0414h) rmw instructions are prohib- ited. bit symbol roms07 roms06 roms05 ro ms04 roms03 roms02 roms01 roms00 read/write w after reset00000000 function patch code (lower 8 bits) bank2 data substitution register h 76543210 romsub2h (0415h) rmw instructions are prohib- ited. bit symbol roms15 roms14 roms13 ro ms12 roms11 roms10 roms09 roms08 read/write w after reset00000000 function patch code (upper 8 bits)
page 193 2007-10-15 tmp91fw60 note 1: the romcmp30/31/32, and romsub3l/3h regist ers do not support read-modify-write operation. note 2: bit0 of the address compare register 0 is read as undefined. bank3 address compare register 0 76543210 romcmp30 (0418h) rmw instructions are prohib- ited. bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? read/write w ? after reset0000000 ? function target rom address (lower 7 bits) ? bank3 address compare register 1 76543210 romcmp31 (0419h) rmw instructions are prohib- ited. bit symbol romc15 romc14 romc13 ro mc12 romc11 romc10 romc09 romc08 read/write w after reset00000000 function target rom address (middle 8 bits) bank3 address compare register 2 76543210 romcmp32 (041ah) rmw instructions are prohib- ited. bit symbol romc23 romc22 romc21 ro mc20 romc19 romc18 romc17 romc16 read/write w after reset00000000 function target rom address (upper 8 bits) bank3 data substitution register l 76543210 romsub3l (041ch) rmw instructions are prohib- ited. bit symbol roms07 roms06 roms05 ro ms04 roms03 roms02 roms01 roms00 read/write w after reset00000000 function patch code (lower 8 bits) bank3 data substitution register h 76543210 romsub3h (041dh) rmw instructions are prohib- ited. bit symbol roms15 roms14 roms13 ro ms12 roms11 roms10 roms09 roms08 read/write w after reset00000000 function patch code (upper 8 bits)
page 194 2007-10-15 tmp91fw60 note 1: the romcmp40/41/42, and romsub4l/4h regist ers do not support read-modify-write operation. note 2: bit0 of the address compare register 0 is read as undefined. bank4 address compare register 0 76543210 romcmp40 (0420h) rmw instructions are prohib- ited. bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? read/write w ? after reset0000000 ? function target rom address (lower 7 bits) ? bank4 address compare register 1 76543210 romcmp41 (0421h) rmw instructions are prohib- ited. bit symbol romc15 romc14 romc13 ro mc12 romc11 romc10 romc09 romc08 read/write w after reset00000000 function target rom address (middle 8 bits) bank4 address compare register 2 76543210 romcmp42 (0422h) rmw instructions are prohib- ited. bit symbol romc23 romc22 romc21 ro mc20 romc19 romc18 romc17 romc16 read/write w after reset00000000 function target rom address (upper 8 bits) bank4 data substitution register l 76543210 romsub4l (0424h) rmw instructions are prohib- ited. bit symbol roms07 roms06 roms05 ro ms04 roms03 roms02 roms01 roms00 read/write w after reset00000000 function patch code (lower 8 bits) bank4 data substitution register h 76543210 romsub4h (0425h) rmw instructions are prohib- ited. bit symbol roms15 roms14 roms13 ro ms12 roms11 roms10 roms09 roms08 read/write w after reset00000000 function patch code (upper 8 bits)
page 195 2007-10-15 tmp91fw60 note 1: the romcmp50/51/52, and romsub5l/5h regist ers do not support read-modify-write operation. note 2: bit0 of the address compare register 0 is read as undefined. bank5 address compare register 0 76543210 romcmp50 (0428h) rmw instructions are prohib- ited. bit symbol romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? read/write w ? after reset0000000 ? function target rom address (lower 7 bits) ? bank5 address compare register 1 76543210 romcmp51 (0429h) rmw instructions are prohib- ited. bit symbol romc15 romc14 romc13 ro mc12 romc11 romc10 romc09 romc08 read/write w after reset00000000 function target rom address (middle 8 bits) bank5 address compare register 2 76543210 romcmp52 (042ah) rmw instructions are prohib- ited. bit symbol romc23 romc22 romc21 ro mc20 romc19 romc18 romc17 romc16 read/write w after reset00000000 function target rom address (upper 8 bits) bank5 data substitution register l 76543210 romsub5l (042ch) rmw instructions are prohib- ited. bit symbol roms07 roms06 roms05 ro ms04 roms03 roms02 roms01 roms00 read/write w after reset00000000 function patch code (lower 8 bits) bank5 data substitution register h 76543210 romsub5h (042dh) rmw instructions are prohib- ited. bit symbol roms15 roms14 roms13 ro ms12 roms11 roms10 roms09 roms08 read/write w after reset00000000 function patch code (upper 8 bits)
page 196 2007-10-15 tmp91fw60 11.3 operation 11.3.1 replacing data two consecutive bytes of data can be replaced for each bank. a two-byte sequence to be replaced must start at an even address. if only a sing le byte at an even or odd address n eed be replaced, set the current masked rom data in the other byte. correction procedure: load the address compare registers (romcmp00 to romcmp02) with the target address where rom data need be replaced. store 2-byte patch code in the romsub0l and romsub0h registers. when the cpu address matches the value stored in the romcmp00 to romcmp02 registers, the program patch logic disables rd output to the masked rom and drives out the code stored in the romsub0l and romsub0h to the internal bus. the cpu thus fetches the patch code. the following shows some examples: figure 11-2 example patch code implementation a. replacing 00h at address ff1230h with aah 76543210 romcmp00 0 0 1 1 0 0 0 0 stores 30 in address compare register 0 for bank0. romcmp01 0 0 0 1 0 0 1 0 stores 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1 1 1 1 stores ff in address compare register 2 for bank0. romsub0l 1 0 1 0 1 0 1 0 store aa in address substitution register low for bank0. romsub0h 0 0 0 1 0 0 0 1 store 11 in address substitution register high for bank0. 1pejkr rgtkrjgtcn 1pejkr4#/ 'zvgtpcnctgc 00h 11h 8gevqtvcdng ff1230h ff1231h replace with aah replace with 11h (same as current value). ffffffh c fe0000h 001000h 000000h 1pejkr41/
page 197 2007-10-15 tmp91fw60 figure 11-3 example patch code implementation figure 11-4 example patch code implementation b. replacing 33h at address ff1233h with bbh 76543210 romcmp00 0 0 1 1 0 0 1 0 stores 32 in address compare register 0 for bank0. romcmp01 0 0 0 1 0 0 1 0 stores 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1 1 1 1 stores ff in address compare register 2 for bank0. romsub0l 0 0 1 0 0 0 1 0 store 22 in address substitution register low for bank0. romsub0h 1 0 1 1 1 0 1 1 store bb in address substitution register high for bank0. c. replacing 44h at address ff1234h with cch and 55h at address ff1235h with ddh 76543210 romcmp00 0 0 1 1 0 1 0 0 stores 34 in address compare register 0 for bank0. romcmp01 0 0 0 1 0 0 1 0 stores 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1 1 1 1 stores ff in address compare register 2 for bank0. romsub0l 1 1 0 0 1 1 0 0 store cc in address substitution register low for bank0. romsub0h 1 1 0 1 1 1 0 1 store dd in address substitution register high for bank0. ff1232h ff1233h ffffffh d fe0000h 001000h 000000h 1pejkr rgtkrjgtcn 1pejkr4#/ 'zvgtpcnctgc 00h 11h 8gevqtvcdng 1pejkr41/ replace with 22h (same as current value). replace with bbh ff1234h ff1235h ffffffh e fe0000h 001000h 000000h 1pejkr rgtkrjgtcn 1pejkr4#/ 'zvgtpcnctgc 00h 11h 8gevqtvcdng 1pejkr41/ replace with cch replace with ddh
page 198 2007-10-15 tmp91fw60 figure 11-5 example patch code implementation d. replacing 77h at address ff1237h with eeh and 88h at address ff1238h with ffh (requiring two banks) 76543210 romcmp00 0 0 1 1 0 1 1 0 stores 36 in address compare register 0 for bank0. romcmp01 0 0 0 1 0 0 1 0 stores 12 in address compare register 1 for bank0. romcmp02 1 1 1 1 1 1 1 1 stores ff in address compare register 2 for bank0. romsub0l 0 1 1 0 0 1 1 0 store 66 in address substitution register low for bank0. romsub0h 1 1 1 0 1 1 1 0 store ee in address substitution register high for bank0. romcmp10 0 0 1 1 1 0 0 0 stores 38 in address compare register 0 for bank1. romcmp11 0 0 0 1 0 0 1 0 stores 12 in address compare register 1 for bank1. romcmp12 1 1 1 1 1 1 1 1 stores ff in address compare register 2 for bank1. romsub1l 1 1 1 1 1 1 1 1 store ff in address substitution register low for bank1. romsub1h 1 0 0 1 1 0 0 1 store 99 in address substitution register high for bank1. 66h 77h 88h 99h ff1236h ff1237h ff1238h ff1239h ffffffh f fe0000h 001000h 000000h 1pejkr rgtkrjgtcn 1pejkr4#/ 'zvgtpcnctgc 8gevqtvcdng 1pejkr41/ replace with 66h (same as current value). replace with eeh replace with ffh replace with 99h (same as current value).
page 199 2007-10-15 tmp91fw60 11.3.2 using an interrupt to cause a branch a wider range of program code can also be fixed using a software interrupt (swi). with a patch code loaded into on-chip ram, the progra m patch logic can be used to replace progr am code at a specified address with a single-byte swi instruction, which causes a branch to the patch program. note that this method can only be used if the original masked rom has been developed with on-chip ram addresses specified as swi vector addresses. correction procedure: load the address compare registers (romcmp00 to romcmp02) with the start address of the program code that is to be fixed. if it is an even address, store an swi instruction code (e.g., swi:f9h) in the rom- subl. if the start address is an odd address, store an swi instruction code in the romsubh and the current rom data at the preceding ev en address in the romsubl. when the cpu address matches the value stored in the romcmp00 to romcmp02 registers, the program patch logic disables rd output to the masked rom and drives out the swi instruction code to the internal bus. upon fetching the swi code, the cpu makes a branch to the internal ram area to ex ecute the preloaded code. at the end of the patch program executed from the in ternal ram, the cpu directly rewrites the saved pc value so that it points to the address follow ing the patch code, and then executes a reti. the following shows an example: example: fixing a program within the range from ff5000h to ff507fh before developing the original masked rom, set the swi1 vector reference address to 001500h (on- chip ram area). use the startup routine to load the patch code to on-chip ram (001500h to 0015efh). store the start address (ff5000h) of the rom area to be fixed in the romcmp00 to romcmp02. store the swi1 instruction code (f9h) in the romsub0l and the current data at ff5001h (aah) in the romsub0h. when the cpu address matches the value stored in romcmp00 to romcmp02, the program patch logic replaces the rom-based code at ff5000h with f9h. the cpu then executes the swi1 instruction, which causes a branch to 001500h in the on-chip ram area. after executing the patch program the cpu finally rewrites the saved pc value to ff5080h and executes a reti.
page 200 2007-10-15 tmp91fw60 figure 11-6 exam ple rom correction 1pejkr rgtkrjgtcn 1pejkr4#/ 'zvgtpcnctgc 1pejkr41/ 55h aah sw1 xgevqt (((* ((* replace the start address with f9h (swi1 instruction code). replace with aah (same as current value). &ghgevkxg ctgc ('* * * ((* ((* ((((* :* ((((* ((((* 8gevqtvcdng 001500h 2cvej rtqitco * n n n n * '(* 2tqitcodqf[ n n n n 4gytkvguvcem reti * '(* 4gvwtphtqo+06 $tcpejecwugfd[59
page 201 2007-10-15 tmp91fw60 12. watchdog timer (runaway detection timer) the tmp91fw60 features a watchdog timer for detecting runaway. the watchdog timer (wdt) is used to return the cpu to normal state when it detects that the cpu has started to malfunction (runaway) due to causes such as noise. when the watchdog timer detects a malfunction, it gene rates a non-maskable interrupt intwd to notify the cpu. connecting the watchdog timer output to the reset pin internally forces a reset.(the level of external reset pin is not changed) 12.1 configuration figure 12-1 is a block diagram of he watchdog timer (wdt). figure 12-1 block diagr am of watchdog timer note: it needs to care designing the total machine set, bec ause watchdog timer can?t operate completely by external noise. binary counter (22 stages) intwd interrupt reguest wdmod wdmod wdmod internal reset internal reset write 4eh write b1h q r s selector reset 2 15 wdt control register wdcr f sys (f fph /2) 2 17 2 19 2 21 reset reset control internal data bus
page 202 2007-10-15 tmp91fw60 12.2 operation the watchdog timer generates an intwd interrupt when the detection time set in the wdmod has elapsed. the watchdog timer must be cleared ?0? by software before an intwd interrupt will be generated. if the cpu malfunctions (e.g., if runaway occu rs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary co unter will overflow and an intwd interrupt will be generated. the cpu will detect malfunction (runaway) due to the intwd interrupt and in this case it is possible to return to the cpu to nor- mal operation by means of an anti-malfunction program. the watchdog timer works immediately after reset. the watchdog timer does not operate in idle1 or stop mode. when the device is in idle2 mode, the operation of wdt depends on the wdmod setting. ensure that wdmod is set before the device enters idle2 mode. the watchdog timer consists of a 22-stage bina ry counter which uses the system clock (f sys ) as the input clock. the binary counter can output f sys /2 15 , f sys /2 17 , f sys /2 19 and f sys /2 21 . figure 12-2 normal mode the runaway is detected when an overflow occurs, and the watchdog timer can reset this device. in this case, the reset time will be between 22 and 29 states (51.2 s at f osch = 20 mhz) as shown in figure 12-3. after a reset, the f sys clock (1 cycle = 1 state) is f fph /2, where f fph is generated by dividing the high-speed oscillator clock (f osch ) by sixteen through the clock gear function. figure 12-3 reset mode n overflow 0 wdt counter wdt clear (software) wdt interrupt write clear code n overflow wdt counter internal reset wdt interrupt 22 to 29 states  (26.1 to 34.4 s at f osch = 27 mhz, f fph = 1.7 mhz)
page 203 2007-10-15 tmp91fw60 12.3 control registers the watchdog timer wdt is controlled by two control registers wdmod and wdcr. 12.3.1 watchdog timer mode register (wdmod) a. setting the detection time for the watchdog timer in this 2-bit register is used for setting the watch dog timer interrupt time used when detecting run- away. after reset, this register is initialized to wdmod = ?00?(2 15 / f sys [s]). b. watchdog timer enable/disab le control register after reset, wdmod is initialized to ?1?, enabling the watchdog timer. to disable the watchdog timer, it is necessary to set this bit to ?0? and to write the disable code (b1h) to the watchdog timer control register wdcr. this makes it difficult for the watchdog timer to be disabled by runaway. however, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting to ?1?. c. watchdog timer out reset connection this register is used to connect the output of the watchdog timer with the internal reset. since wdmod is initialized to ?0? on reset, a reset by the watchdog timer will not be per- formed. 12.3.2 watchdog timer c ontrol register (wdcr) this register is used to disable and clear the binary counter for the watchdog timer. ? disable control the watchdog timer can be disabled by clearin g wdmod to ?0? and then writing the disable code (b1h) to the wdcr register. ? enable control set wdmod to ?1?. ? watchdog timer clear control to clear the binary counter and cause counting to resume, write th e clear code (4 eh) to the wdcr register. wdmod 0 ? ? x x ? ? 0 clear wdmod to ?0?. wdcr 1 0 1 1 0 0 0 1 write the disable code (b1h). wdcr 01001110 write the clear code (4eh).
page 204 2007-10-15 tmp91fw60 watchdog timer mode register 76543210 wdmod (0300h) bit symbol wdte wdtp1 wdtp0 ? ? i2wdt rescr ? read/write r/w r/w ? ? r/w r/w after reset100??000 function wdt control 1: enable select detecting time 00: 2 15 /f sys 01: 2 17 /f sys 10: 2 19 /f sys 11: 2 21 /f sys idle2 control reset control always write ?0?. watchdog timer out control rescr 0? 1 connect wdt out to a internal reset idle2 control i2wdt 0stop 1 operation watchdog timer detection time @fc = 20 mhz, fs = 32.768 khz syscr1 system clock selection syscr1 gear value watchdog timer detection time wdmod 00 01 10 11 1(fs) xxx 2.0 s 8.0 s 32.0 s 128.0 s 0(fc) 000 (fc) 3.28 ms 13.11 ms 52.43 ms 209.72 ms 001 (fc/2) 6.55 ms 26.21 ms 104.86 ms 419.43 ms 010(fc/4) 13.11 ms 52.43 ms 209.72 ms 838.86 ms 011 (fc/8) 26.21 ms 104.86 ms 419.43 ms 1677.72 ms 100 (fc/16) 52.43 ms 209.72 ms 838.86 ms 3355.44 ms watchdog timer enable/disable control wdte 0 disabled 1 enabled watchdog timer control register 76543210 wdcr (0301h) rmw instructions are prohib- ited. bit symbol - read/write w after reset - function b1h: wdt disable code 4eh: wdt clear code disable/clear wdt b1h disable code 4eh clear code others don?t care
page 205 2007-10-15 tmp91fw60 13. special timer for clock the tmp91fw60 includes a timer that is used for a clock operation. an interrupt (intrtc) can be generated each 0.0625 [s] or 0.125 [s] or 0.25 [s] or 0.50 [s] by using a low fre- quency clock of 32.768 khz. a clock function can be easily used. in addition, intrtc can return from each standby mode except stop mode. a special timer for clock can operate in all mode s in which a low-frequency oscillation is operated. the special timer for clock is contro lled by the special timer for clock co ntrol register (rtccr) as shown in. 13.1 configuration figure 13-1 blo ck diagram for special timer for clock special timer for clock control register 76543210 rtccr (0310h) bit symbol ????? rtcsel1 rtcsel0 rtcrun read/write r/w ???? r/w r/w after reset 0 ???? 000 function always write ?0?. ???? 00: 2 14 /fs 01: 2 13 /fs 10: 2 12 /fs 11: 2 11 /fs 0: stop & clear 1: count counting operation 0 stop & clear 1 count interrupt generation cycle (fs = 32.768 khz) 00 0.50 s 11 0.25 s 10 0.125 s 11 0.0625 s interrupt request intrtc fs (32.768 khz) run/ clear 2 11 rtccr rtccr 2 12 2 13 2 14 14-stage binary counter selector
page 206 2007-10-15 tmp91fw60 14. flash memory the tmp91fw60 incorporates flash memo ry that can be electrically erased and programmed using a single 5v power supply. the flash memory is programmed and erased using je dec-standard commands. after a program or erase com- mand is input, the corresponding operation is automatically performed internally. erase operations can be performed by the entire chip (chip erase) or on a sector basis (sector erase). the configuration and oper ations of the flash memory are described below. 14.1 features 14.2 block diagram figure 14-1 block diagram of flash memory unit power supply voltage for program/erase operations sector size - vcc = 4.75 to 5.25 v - 8kbytes 16 (t opr = -10 to 40 c, fc = 4 to 20mhz) mode control configuration - jede c-standard commands - 64k 16 bits (128 k bytes) programming method functions - on-board programming - single-word programming - parallel programmer - chip erase security - sector erase - write protection - data polling / toggle bit - read protection +pvgtpcncfftguudwu 41/ eqpvtqnngt  oqfg eqpvtqn  oqfg ugvvkpirkp %qpvtqn  &cvc (ncujogoqt[ %qnwopfgeqfgt5gpugcor  &cvcncvej  #fftguuncvej  'tcugugevqtfgeqfgt  %qpvtqn ektewkv
kpenwfkpi cwvqocvke ugswgpeg eqpvtqn ektewkv %qoocpf tgikuvgt          (ncujogoqt[egnnu    -$     4qyfgeqfgt  #fftguu +pvgtpcnfcvcdwu +pvgtpcneqpvtqndwu
page 207 2007-10-15 tmp91fw60 14.3 operation modes 14.3.1 overview the following three types of operation modes are availa ble to control program/erase operations on the flash memory. of the modes listed in table 14-1, the internal flash memory can be pr ogrammed in user boot mode, single boot mode and programmer mode. the mode in which the flash memory can be programmed/erased while mounted on the user board is defined as the on-board programming mode. of the modes listed above, single boot mode and user boot mode are classified as on-board programming modes. single bo ot mode supports toshiba's proprietary programming/ erase method using serial i/o. user boot mode (withi n single chip mode) allows the flash memory to be pro- grammed/erased by a user-specified method. programmer mode is provided with a read protect function which prohibits reading of rom data. by enabling the read protect function upon completion of programming, the user can protect rom data from being read by third parties. table 14-1 description of operation modes operation mode name description single chip mode after reset release, the device starts up from the internal flash memory. single chip mode is further divided into two m odes: ?normal mode? is a mode in which user application programs are executed, and ?user boot mode? is used to program the flash memory on-board. the means of switching between these two modes can be set by the user as desired. for exam- ple, it can be set so that port 00 = '1' selects normal mode and port 00 = '0' selects user boot mode. the user must include a routine to handle mode switching in a user application program. normal mode in this mode, the device starts up from a user application program. user boot mode in this mode, the flash memory can be programmed by a user-specified method. single boot mode after reset release, the device starts up from the internal boot rom (mask rom). the boot rom includes an algorithm which allows a pr ogram for programming/erasing the flash memory on-board via a serial port to be transferred to the device's internal ram. the transferred pro- gram is then executed in the internal ram so that the flash memory can be programmed/erased by receiving data from an external host and issuing program/erase commands. programmer mode this mode enables the internal flash memory to be programmed/erased using a general-pur- pose programmer. for programmers that can be us ed, please contact your local toshiba sales representative.
page 208 2007-10-15 tmp91fw60 the operation mode single chip mode, single boot m ode or programmer mode is determined during reset by externally setting the input levels on the am0, am1 and boot (emu0) pins. except in programmer mode which is entered with reset held at ?0?, the cpu will start operating in the selected mode after the reset state is released. once the operati on mode has been set, make sure that the input levels on the mode setting pins are not changed during operation.table 14-2 shows how to set each operation mode, and figure 14-2 shows a mode transition diagram. note:although emu0 is an output pin, it becomes an input pi n with pull-up resistor only during a reset. after a reset, emu0 operates as follows depending on the operation mode. >single chip mode : output pin with pull-up resistor >single boot mode : pull-up (input gate is invalid, and output gate is in high impedance.) note: numbers in ( ) correspond to the operation mode pin settings shown in table 14-2. figure 14-2 mode transition diagram 14.3.2 reset operation to reset the device, hold the reset input at ?0? for at least 10 system clocks while the power supply voltage is within the rated operating voltage range and the inte rnal high-frequency oscillator is oscillating stably. for details, refer to ?reset of cpu?. table 14-2 operation mode pin settings operation mode input pins reset boot (emu0) am1 am0 (1) single chip mode (normal or user boot mode) rising edge open 1 1 (2) single boot mode 0 1 1 (3) programmer mode 0 - 1 0 1pdqctfrtqitcookpi  oqfg  4'5'6  4'5'6 
 

   5ykvejkpiogvjqf vqdgugvd[wugt  5kpingejkroqfg  4gugvuvcvg 
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  9  4'5'6  0qtocnoqfg  7ugt$qqv oqfg  5kping$qqv  oqfg  2tqitcoogt oqfg
page 209 2007-10-15 tmp91fw60 14.3.3 memory map for each operation mode in this product, the memory map varies with operatio n mode. the memory map and sector address ranges for each operation mode are shown below. figure 14-3 memory map for each operation mode  *  *  ((((((*    4gugtxgf   *  *  *  ('*  ((((*  ((((((*  +pvgtpcn+1 +pvgtpcn 4#/ -$   'zvgtpcnogoqt[ +pvgtpcn (ncuj41/ -$  
+pvgttwrvxgevqt$  (((*  *  *  *  *   ((((*  ((((((*  *
m &?   ]+? (ncuj41/  +pvgtpcn +1   'zvgtpcnogoqt[ 'zvgtpcnogoqt[ +pvgtpcn$qqv41/  -$   
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page 210 2007-10-15 tmp91fw60 table 14-3 sector address ranges for each operation mode single chip mode single boot mode sector-0 fe0000h to fe1fffh 10000h to 11fffh sector-1 fe2000h to fe3fffh 12000h to 13fffh sector-2 fe4000h to fe5fffh 14000h to 15fffh sector-3 fe6000h to fe7fffh 16000h to 17fffh sector-4 fe8000h to fe9fffh 18000h to 19fffh sector-5 fea000h to febfffh 1a000h to 1bfffh sector-6 fec000h to fedfffh 1c000h to 1dfffh sector-7 fee000h to feffffh 1e000h to 1ffffh sector-8 ff0000h to ff1fffh 20000h to 21fffh sector-9 ff2000h to ff3fffh 22000h to 23fffh sector-10 ff4000h to ff5fffh 24000h to 25fffh sector-11 ff6000h to ff7fffh 26000h to 27fffh sector-12 ff8000h to ff9fffh 28000h to 29fffh sector-13 ffa000h to ffbfffh 2a000h to 2bfffh sector-14 ffc000h to ffdfffh 2c000h to 2dfffh sector-15 ffe000h to ffffffh 2e000h to 2ffffh
page 211 2007-10-15 tmp91fw60 14.4 single boot mode in single boot mode, the internal boot rom (mask rom) is activated to transfer a program/erase routine (user- created boot program) from an external source into the inte rnal ram. this program/erase routine is then used to pro- gram/erase the flash memory. in this mode, the internal boot rom is mapped into an area containing the interrupt vector table, in which the boot rom pr ogram is executed. the flash memory is mapped into an address space differ- ent from the one into which the boot rom is mapped (see figure 14-3). the device's sio (sio1) and the contro ller are connected to transfer the pr ogram/erase routine from the controller to the device's internal ram. this pr ogram/erase routine is then executed to program/erase the flash memory. the program/erase routine is executed by sending commands and write data from the controller. the communications protocol between the device and the controller is describe d later in this manual. before the program/erase routine can be transferred to the ram, user passwor d verification is performed to ensure the security of user rom data. if the password is not verified co rrectly, the ram transfer operation cannot be performed. in single boot mode, disable interrupts and use the interrupt request fl ags to check for an interrupt request. note: do not change to another operation mode in the program/erase routine.
page 212 2007-10-15 tmp91fw60 14.4.1 using the program/e rase algorithm in t he internal boot rom (step-1)environment setup since the program/erase routine and write data are transferred via si o (sio1), connect the device's sio (sio1) and the controller on the board. the user must prepare the program/erase routine (a) on the con- troller. (step-2) starting up the internal boot rom release the reset with the relevant input pins set for entering single boot mode. when the internal boot rom starts up, the program/erase rout ine (a) is transferred from the cont roller to the internal ram via sio according to the communications proced ure for single boot mode. before th is can be carried out, the password entered by the user is verified against the password writt en in the user application program. (if the flash mem- ory has been erased, 12 bytes of ? 0xff? are used as the password.) 
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page 213 2007-10-15 tmp91fw60 (step-3) copying the progra m/erase routine to the ram after password verification is completed, the boot rom copies the program/erase routine (a) from the con- troller to the ram using serial communications. the pr ogram/erase routine must be stored within the ram address range of 001000h to 002dffh. (step-4) executing the progra m/erase routine in the ram control jumps to the program/erase routine (a) in the ram. if necessary, the old user application program is erased (sector erase or chip erase). note 1: the boot rom is provided with an erase command, which enables the entire chip to be erased from the controller without using the program/erase routine. note 2: if it is necessary to erase data on a sector basis, incorporate the necessary code in the program/erase rou- tine. 
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page 214 2007-10-15 tmp91fw60 (step-5) copying the new user application program the program/erase routine (a) loads th e new user application program from the controller into the erased area of the flash memory. in the example below, the new user application program is transferred under the same communications con- ditions as those used for transferring the program/erase routine. however, after the program/erase routine has been transferred, this routine can be used to change th e transfer settings (data bus an d transfer source). config- ure the board hardware and program/erase routine as desired. (step-6) executing the new user application program after the programming operation has been completed, tu rn off the power to the board and remove the cable connecting the device and the controll er. then, turn on the power again and start up the device in single chip mode to execute the new user application program. 
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page 215 2007-10-15 tmp91fw60 14.4.2 connection examples for single boot mode in single boot mode the flash memory is programme d by serial transfer. therefore, on-board programming is performed by connecting the device's sio (sio1) a nd the controller (programming tool) and sending com- mands from the controller to the device. figure 14-4 shows an example of connection between the target board and a programming controller. figure 14-5 shows an example of connection between the target board and an rs232c board. figure 14-4 example of connection with an external c ontroller in single boot mode &8%% 8%% 45% 41/ /qfgeqpvtqn 2tqitco eqpvtqnngt 8%%  8%% 4gi 1p$qctf2tqitcookpi%qpvtqnngt 4'5'6 $116 /%7 6ctigvdqctf qrgtcvkqp 4'5'6 $116
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page 217 2007-10-15 tmp91fw60 14.4.3 mode setting to perform on-board programming, the device must be started up in single boot mode by setting the input pins as shown below. am0,am1= 1 boot = 0 reset = 0 1 set the am0, am1, and boot pins as shown above with the reset pin held at ?0?. then, setting the reset pin to ?1? will start up the device in single boot mode. 14.4.4 memory maps figure 14-6 shows a comparison of the memory map for normal mode (in single chip mode) and the mem- ory map for single boot mode. in single boot mode, the flash memory is mapped to addresses 10000h to 2ffffh (physical addresses) and the boot rom (mask rom) is mapped to addresses fff000h to ffffffh. figure 14-6 comparison of memory maps 5kping%jkroqfg 5kping$qqvoqfg 000000h 001000h 003000h fe0000h ffff00h ffffffh fff000h 000000h 001000h 010000h 030000h ffff00h ffffffh 003000h (
m&? ) ]+? flash rom internal i/o internal ram 8kb external memory internal flash rom 128kb internal i/o internal ram 8kb external memory external memory internal boot rom 4kb internal flash rom 128kb (interrupt vector 256b) (interrupt vector 256b)
page 218 2007-10-15 tmp91fw60 14.4.5 interface specifications the sio communications format in single boot mode is shown below. the device supports the uart (asyn- chronous communications) serial operation mode. to perform on-board programming, the same communi cations format must also be set on the programming controller's side. note: unused pins are in the initial state after reset release. uart (asynchronous) communications - communications channel : sio channel 1(for the pins be used, see table 14-4 ) - serial transfer mode : uart (asynchronous communications) mode - data length : 8 bits - parity bit : none - stop bit : 1 bit - baud rate : see table 14-5 , table 14-6 table 14-4 pin connections pins uart power sup- ply pins dvcc dvss mode set- ting pins am1,am0 boot reset pin reset communi- cations pins txd1 rxd1 table 14-5 baud rate table sio transfer rate (bps) uart 115200 57600 38400 19200 9600
page 219 2007-10-15 tmp91fw60 reference frequency: the frequency of the high-speed oscillation circ uit that can be used in single boot mode. to program the flash memory using single boot mode, one of the reference frequencies must be selected as a high-speed clock. supported range: the range of clock frequencies that are detected as each reference frequency. it may not be possible to perform single boot operations at clock fr equencies outside of the supported range. note:to automatically detect the reference frequency (micro controller clock frequency), the transfer baud rate error of the flash memory programming controller and the oscillation frequency error must be within ?1.5 %, + 2% in total. table 14-6 correspondence betw een operating frequency and baud rate in single boot mode 115200 error (%) - - - - 0 - - - baud rate (bps) - - - - 115200 - - - 57600 error (%) - - - - 0 - 0 - baud rate (bps) - - - - 57600 - 57600 - 38400 error (%) - +1.73 - 0 0 - - +1.73 baud rate (bps) - 39063 - 38400 38400 - - 39063 19200 error (%) - +1.73 0 0 0 +0.16 0 +1.73 baud rate (bps) - 19531 19200 19200 19200 19231 19200 19531 9600 error (%) +0.16 +1.73 0 0 0 +0.16 0 +1.73 baud rate (bps) 9615 9766 9600 9600 9600 9615 9600 9766 reference baud rate (bps) supported range (mhz) 7.87 to 8.14 9.69 to 10.02 10.90 to 11.28 12.11 to 12.53 14.53 to 15.04 15.74 to 16.29 18.16 to 18.80 19.37 to 20.05 reference frequency (mhz) 8 10 11.0592 12.288 14.7456 16 18.4320 20
page 220 2007-10-15 tmp91fw60 14.4.6 data transfer formats table 14-7 to table 14-12 show the operation command data and the data transfer format for each operation mode. table 14-7 operation command data operation command data operation mode 10h ram transfer 20h flash memory sum 30h product information read 40h flash memory chip erase 60h flash memory protect set
page 221 2007-10-15 tmp91fw60 table 14-8 transfer format of single boot program [ram transfer] transfer byte number transfer data from controller to device baud rate transfer data from device to controller boot rom 1st byte baud rate setting uart 86h desired baud rate #1 #1 for the desired baud rate setting, see table 14-6 . - 2nd byte - ack response to baud rate setting normal (baud rate ok) >uart 86h (if the desired baud rate cannot be set, operation is terminated.) 3rd byte operation command data (10h) - 4th byte - ack response to operation command #2 normal 10h error x1h protection applied #3 x6h communications error x8h #2 after sending an error response, the device waits for operation command data (3rd byte). #3 when read protection or write protection is applied, the device aborts the received operation command and waits for the next operation command data (3rd byte). 5th byte to 16th byte password data (12 bytes) (02fef4h to 02feffh) - 17th byte checksum value for 5th to 16th bytes - 18th byte - ack response to checksum value #2 normal 10h error 11h communications error 18h 19th byte ram storage start address 31 to 24 #4 #4 the data to be transferred in the 19th to 25th bytes should be programmed within the ram address range of 001000h to 002dffh (7.5 kbytes). - 20th byte ram storage start address 23 to 16 #4 - 21th byte ram storage start address 15 to 8 #4 - 22th byte ram storage start address 7 to 0 #4 - 23th byte ram storage byte count 15 to 8 #4 - 24th byte ram storage byte count 7 to 0 #4 - 25th byte checksum value for 19th to 24th bytes #4 - 26th byte - ack response to checksum value #2 normal 10h error 11h communications error 18h 27th byte to (m)th byte ram storage data - (m+1)th byte checksum value for 27th to m'th bytes - (m+2)th byte - ack response to checksum value #2 normal 10h error 11h communications error 18h ram (m+3)th byte - jump to ram storage start address
page 222 2007-10-15 tmp91fw60 table 14-9 transfer format of single boot program [flash memory sum] transfer byte number transfer data from controller to device baud rate transfer data from device to controller boot rom 1st byte baud rate setting uart 86h desired baud rate #1 #1 for the desired baud rate setting, see table 14-6 . - 2nd byte - ack response to baud rate setting normal (baud rate ok) >uart 86h (if the desired baud rate cannot be set, operation is terminated.) 3rd byte operation command data (20h) - 4th byte - ack response to checksum value #2 normal 20h error x1h communications error x8h #2 after sending an error response, the device waits for operation command data (3rd byte). 5th byte - sum (upper) 6th byte - sum (lower) 7th byte - checksum value for 5th and 6th bytes 8th byte (wait for the next operation command data) -
page 223 2007-10-15 tmp91fw60 table 14-10 transfer format of single boot program [product information read](1/2) transfer byte number transfer data from controller to device baud rate transfer data from device to controller boot rom 1st byte baud rate setting uart 86h desired baud rate #1 - 2nd byte - ack response to baud rate setting normal (baud rate ok) >uart 86h (if the desired baud rate cannot be set, operation is terminated.) 3rd byte operation command data (30h) - 4th byte - ack response to operation command #2 normal 30h error x1h communications x8h 5th byte - flash memory data (address 02fef0h) 6th byte - flash memory data (address 02fef1h) 7th byte - flash memory data (address 02fef2h) 8th byte - flash memory data (address 02fef3h) 9th byte to 20th byte - part number (ascii code, 12 bytes) 'tmp91fw60 _ _ _ ' (from 9th byte) 21th byte to 24th byte - password comparison start address (4 bytes) f4h, feh, 02h, 00h (from 21st byte) 25th byte to 28th byte - ram start address (4 bytes) 00h, 10h, 00h, 00h (from 25th byte) 29th byte to 32th byte - ram (user area) end address (4 bytes) ffh, 2dh, 00h, 00h (from 29th byte) 33th byte to 36th byte - ram end address (4 bytes) ffh, 2fh, 00h, 00h (from 33rd byte) 37th byte to 40th byte - dummy data (4 bytes) 00h,00h,00h,00h (from 37th byte) 41th byte to 44th byte - dummy data (4 bytes) 00h, 00h, 00h, 00h (from 41st byte) 45th byte to 46th byte - fuse information (2 bytes from 45th byte) read protection/write protection 1) applied/applied : 00h, 00h 2) not applied/applied : 01h, 00h 3) applied/not applied : 02h, 00h 4) not applied/not applied : 03h, 00h 47th byte to 50th byte - flash memory start address (4 bytes) 00h, 00h, 01h, 00h (from 47th byte) 51th byte to 54th byte - flash memory end address (4 bytes) ffh, ffh, 02h, 00h (from 51st byte) 55th byte to 56th byte - number of sectors in flash memory (2 bytes) 10h, 00h (from 55th byte) 57th byte to 60th byte - start address of flash memory sectors of the same size (4 bytes) 00h, 00h, 01h, 00h (from 57th byte)
page 224 2007-10-15 tmp91fw60 61th byte to 64th byte - size (in half words) of flash memory sectors of the same size (4 bytes) 00h, 10h, 00h, 00h (from 61st byte) 65th byte - number of flash memory sectors of the same size (1 byte) 10h 66th byte - checksum value for 5th to 65th bytes 67th byte (wait for the next operation command data) - #1 for the desired baud rate setting, see table 14-6 . #2 after sending an error response, the device waits for operation command data (3rd byte). table 14-11 transfer format of single boot program [flash memory chip erase] transfer byte number transfer data from controller to device baud rate transfer data from device to controller boot rom 1st byte baud rate setting uart 86h desired baud rate #1 #1 for the desired baud rate setting, see table 14-6 . - 2nd byte - ack response to baud rate setting normal (baud rate ok) >uart 86h (if the desired baud rate cannot be set, operation is terminated.) 3rd byte operation command data (40h) - 4th byte - ack response to operation command #2 normal 40h error x1h communications x8h #2 after sending an error response, the device waits for operation command data (3rd byte). 5th byte erase enable command data (54h) - 6th byte - ack response to operation command #2 normal 54h error x1h communications x8h 7th byte - ack response to erase command normal 4fh error 4ch 8th byte - ack response normal 5dh error 60h 9th byte (wait for the next operation command data) - table 14-10 transfer format of single boot program [product information read](2/2) transfer byte number transfer data from controller to device baud rate transfer data from device to controller
page 225 2007-10-15 tmp91fw60 table 14-12 transfer format of single boot program [flash memory protect set] transfer byte number transfer data from controller to device baud rate transfer data from device to controller boot rom 1st byte baud rate setting uart 86h desired baud rate #1 #1 for the desired baud rate setting, see table 14-6 . - 2nd byte - ack response to baud rate setting normal (baud rate ok) >uart 86h (if the desired baud rate cannot be set, operation is terminated.) 3rd byte operation command data (60h) - 4th byte - ack response to operation command #2 normal 60h error x1h communications x8h #2 after sending an error response, the device waits for operation command data (3rd byte). 5th byte to 16th byte password data (12 bytes) (02fef4h to 02feffh) - 17th byte checksum value for 5th to 16th bytes - 18th byte - ack response to checksum value #2 normal 60h error 61h communications 68h 19th byte - ack response to protect set command normal 6fh error 6ch 20th byte - ack response normal 31h error 34h 21th byte (wait for the next operation command data) -
page 226 2007-10-15 tmp91fw60 14.4.7 boot program when the device starts up in single boot mode, the boot program is activated. the following explains the commands that are used in the boot program to communicate w ith the controller when the device starts up in single boot mode. use this information for creating a controller for using single boot mode or for building a user boot environment. 1. ram transfer command in ram transfer, data is transferred from the co ntroller and stored in the device's internal ram. when the transfer completes normally, the boot pr ogram will start running th e transferred user pro- gram. up to 7.5 kbytes of data can be transferre d as a user program. (this limit is implemented in the boot program to protect the st ack pointer area.) the user progra m starts executing from the ram storage start address. this ram transfer function enables a user-created program/erase routine to be executed, allowing the user to implement their ow n on-board programming method. to perform on-board programming with a user program, the flash memory command sequences (see section 14.6) must be used. after the ram transfer command has been completed, the entire internal ram area can be used. if read protection or write protection is applied on the device or a password error occurs, this com- mand will not be executed. 2. flash memory sum command this command calculates the sum of 128 kbytes of data in the flash memory and returns the result. there is no operation command available to the boot program for reading data from the entire area of the flash memory. instead, this flash me mory sum command can be used. reading the sum value enables revision management of the application program. 3. product information read command this command returns the information about the device including its part number and memory details stored in the flash memory at addresse s 02fef0h to 02fef3h. th is command can also be used for revision management of the application program. 4. flash memory chip erase command this command erases all the sector s in the flash memory. if read protection or write protection is applied on the device, all the sectors in the flash me mory are erased and the read protection or write protection is cleared. since this command is also used to restore the operation of the boot program when the password is forgotten, it does not include password verification. 5. flash memory protect set command this command sets both read pr otection and write protection on the device. however, if a pass- word error occurs, this comm and will not be executed. when read protection is set, the flash memory cannot be read in programmer mode. when write protection is set, the flash memory cannot be written in programmer mode.
page 227 2007-10-15 tmp91fw60 14.4.8 ram transfer command see table 14-8. 1. from the controller to the device the data in the 1st byte is used to determine the baud rate. the 1st byte is transferred with receive operation disabled (sc1mod0 = 0). (the baud rate is determined using an internal timer.) to communicate in uart mode send the value 86h from the controller to the target board using uart settings at the desired baud rate. if the serial operation mode is de termined as uart, the device checks to see whether or not the desired baud rate can be set. if the device determines that the desired baud rate cannot be set, operation is terminated and no communications can be established. 2. from the device to the controller the data in the 2nd byte is the ack response returned by the device for the serial operation mode setting data sent in the 1st byte. if the data in the 1st byte is found to signify uart and the desired baud rate can be set, the device returns 86h. baud rate determination the device determines whether or not the desired baud rate can be set. if it is found that the baud rate can be set, the boot program rewrites the br1cr and br1add values and returns 86h. if it is found that the desired baud rate cannot be set, operation is terminated and no data is returned. the controller sets a time-out time (5 seconds) after it has finished sending the 1st byte. if the contro ller does not receive the response (86h) normally w ithin the time-out time, it should be considered that the device is unable to communicate. receive operation is enabled (sc1mod0 = 1) before 86h is written to the transmission buffer. 3. from the controller to the device the data in the 3rd byte is op eration command data. in this cas e, the ram transfer command data (10h) is sent from the controller to the device. 4. from the device to the controller the data in the 4th byte is the ack response to the operation command data in the 3rd byte. first, the device checks to see if the received data in the 3rd byte contains any error. if a receive error is found, the device returns the ack response data fo r communications error (bit 3) x8h and waits for the next operation command data (3rd byte). the uppe r four bits of the ack response data are unde- fined (they are the upper four bits of the immediately preceding operation command data). next, if the data received in th e 3rd byte correspond s to one of the oper ation commands given in table 14-7, the device echoes back the received data (ack response for normal reception). in the case of the ram transfer command, if read or wr ite protection is not applied, 10h is echoed back and then execution branches to the ram transfer processing routine. if protection is applied, the device returns the corresponding ack response data (bit 2/1) x6h and waits for the next operation command data (3rd byte). the upper four bits of the ack response data are undefined. (they are the upper four bits of th e immediately preceding op eration command data.) after branching to the ram transf er processing routine, the device checks the data in the password area. for details, see " 14.4.15 password ". if the data in the 3rd byte does not correspond to any operation command, the device returns the ack response data for operation command error (b it0) x1h and waits for the next operation com- mand data (3rd byte). the upper four bits of the ack response data are undefined. (they are the upper four bits of th e immediately preceding op eration command data.)
page 228 2007-10-15 tmp91fw60 5. from the controller to the device the 5th to 16th bytes contain password data (12 bytes). the data in the 5th to 16th bytes is verified against the data at addresses 02fef4h to 02feffh in the flash memory, respectively. 6. from the controller to the device the 17th byte contains checksum data. the checksum data sent by the controller is the two's complement of the lower 8-bit value obtained by summing the data in the 5th to 16th bytes by unsigned 8-bit addition (ignoring any overflow). for details on checksum, see " 14.4.17 how to calculate checksum ". 7. from the device to the controller the data in the 18th byte is the ack response data to the 5th to 17th bytes (ack response to the checksum value). the device first checks to see whet her the data received in the 5th to 17th bytes contains any error. if a receive error is found, the device return s the ack response data for commu- nications error (bit 3) 18h and waits for the next operation command data (3rd byte). the upper four bits of the ack response data are the upper four bits of the immediatel y preceding operation com- mand data, so the value of these bits is ?1?. next, the device checks the checksum data in the 17th byte. this check is made to see if the lower 8-bit value obtained by summing the data in the 5th to 17th bytes by unsigned 8-bit addition (ignoring any overflow) is 00h. if the value is not 00h, the device returns the ack response data for checksum error (bit 0) 11h and waits for the next operation command data (3rd byte). finally, the device examines the result of password verification. if all the data in the 5th to 16th bytes is not verified correctly, the device return s the ack response data for password error (bit 0) 11h and waits for the next operation command data (3rd byte). if no error is found in all the above checks, the device returns the ack response data for normal reception 10 h. 8. from the controller to the device the data in the 19th to 22nd bytes indicates the ra m start address for storing block transfer data. the 19th byte corresponds to address bits 31 to 24, the 20th byte to address bits 23 to 16, the 21st byte to address bits 15 to 8, and the 22nd byte to address bits 7 to 0. 9. from the controller to the device the data in the 23rd and 24th byt es indicates the number of bytes to be transferred. the 23rd byte corresponds to bits 15 to 8 of the transfer byte co unt and the 24th byte corresponds to bits 7 to 0. 10. from the controller to the device the data in the 25th byte is checksum data. th e checksum data sent by the controller is the two's complement of the lower 8-bit value obtained by summing the data in the 19th to 24th bytes by unsigned 8-bit addition (ignoring any overflow). for details on checksum, see " 14.4.17 how to calculate checksum ". note: the data in the 19th to 25th bytes should be placed within addresses 001000h to 002dffh (7.5kbytes) in the internal ram.
page 229 2007-10-15 tmp91fw60 11. from the device to the controller the data in the 26th byte is the ack response data to the data in the 19th to 25th bytes (ack response to the checksum value). the device first checks to see whether the data r eceived in the 19th to 25 th bytes contains any error. if a receive error is found, the device retu rns the ack response data for communications error (bit 3) 18h and waits for the next operation command (3rd byte). the upper four bits of the ack response data are the upper four bits of the immediately preceding operation command data, so the value of these bits is ?1?. next, the device checks the checksum data in the 25th byte. this check is made to see if the lower 8-bit value obtained by summing the data in the 19th to 25th bytes by unsigned 8-bit addition (ignoring any overflow) is 00h. if the value is not 00h, the device returns the ack response data for checksum error (bit 0) 11h and waits for the next operation command data (3rd byte). 12. from the controller to the device the data in the 27th to m'th bytes is the data to be stored in the ram. this data is written to the ram starting at the address specified in the 19th to 22nd bytes. the number of bytes to be written is specified in the 23rd and 24th bytes. 13. from the controller to the device the data in the (m+1)th byte is checksum data . the checksum data sent by the controller is the two's complement of the lower 8-bit value obtained by summing the data in the 27th to m'th bytes by unsigned 8-bit addition (ignoring any overflow). for details on checksum, see " 14.4.17 how to calculate checksum ". 14. from the device to the controller the data in the (m+2)th byte is the ack response data to the 27th to (m+1)th bytes (ack response to the checksum value). the device first checks to see whether the data in th e 27th to (m+1)th byte contains any error. if a receive error is found, the device returns the ack response data for communications error (bit 3) 18h and waits for the next operat ion command (3rd byte). the upper four bits of the ack response are the upper four bits of the immediately preceding operation comma nd data, so the value of these bits is ?1?. next, the device checks the checksum data in the (m +1)th byte. this check is made to see if the lower 8-bit value obtained by summing the data in the 27th to (m+1)th bytes by unsigned 8-bit addi- tion (ignoring any overflow) is 00h. if the valu e is not 00h, the device returns the ack response data for checksum error (bit 0) 11h and waits for the next operation command data (3rd byte). if no error is found in all the above checks, the device returns the ack response data for normal reception 10h. 15. from the device to the controller if the ack response data in the (m+2)th byte is 10h (normal reception), the boot program then jumps to the ram start address sp ecified in the 19th to 22nd bytes.
page 230 2007-10-15 tmp91fw60 14.4.9 flash memory sum command see table 14-9. 1. the data in the 1st and 2nd bytes is the same as in the case of th e ram transfer command. 2. from the controller to the device the data in the 3rd byte is operation comm and data. the flash memory sum command data (20h) is sent here. 3. from the device to the controller the data in the 4th byte is the ack response data to the operation command data in the 3rd byte. the device first checks to see if the data in the 3rd byte contains any erro r. if a receive error is found, the device returns the ack response data fo r communications error (bit 3) x8h and waits for the next operation command data (3rd byte). the uppe r four bits of the ack response data are unde- fined. (they are the upper four bits of the immediately pr eceding operation command data.) then, if the data in the 3rd byte corresponds to one of the operation command values given in table 14-7, the device echoes back the received data (ack respons e for normal reception). in this case, 20h is echoed back and execu tion then branches to the flas h memory sum processing routine. if the data in the 3rd byte does not correspond to any operation command, the device returns the ack response data for operation command error (b it 0) x1h and waits for the next operation com- mand data (3rd byte). the upper four bits of the ack response data are undefined. (they are the upper four bits of th e immediately preceding op eration command data.) 4. from the device to the controller the data in the 5th and 6th bytes is the upper and lower data of the sum value, respectively. for details on sum, see " 14.4.16 how to calculate sum ". 5. from the device to the controller the data in the 7th byte is checksum data. this is the two's complement of the lower 8-bit value obtained by summing the data in the 5th and 6th bytes by unsigned 8-bit addition (ignoring any overflow). 6. from the controller to the device the data in the 8th byte is the next operation command data.
page 231 2007-10-15 tmp91fw60 14.4.10product information read command see table 14-10. 1. the data in the 1st and 2nd bytes is the same as in the case of th e ram transfer command. 2. from the controller to the device the data in the 3rd byte is operation command data. the product inform ation read command data (30h) is sent here. 3. from the device to the controller the data in the 4th byte is the ack response data to the operation command data in the 3rd byte. the device first checks to see if the data in the 3rd byte contains any erro r. if a receive error is found, the device returns the ack response data fo r communications error (bit 3) x8h and waits for the next operation command data (3rd byte). the uppe r four bits of the ack response data are unde- fined. (they are the upper four bits of the immediately pr eceding operation command data.) then, if the data in the 3rd byte corresponds to one of the operation command values given in table 14-7, the device echoes back the received data (ack respons e for normal reception). in this case, 30h is returned and executi on then branches to the product information read processing rou- tine. if the data in the 3rd byte does not correspond to any operation command, the device returns the ack response data for operation command error (b it 0) x1h and waits for the next operation com- mand data (3rd byte). the upper four bits of the ack response data are undefined. (they are the upper four bits of th e immediately preceding op eration command data.) 4. from the device to the controller the data in the 5th to 8th bytes is the data stor ed at addresses 02fef0h to 02fef3h in the flash memory. by writing the id information of software at these addresses, the version of the software can be managed. (for example, 0002h can indi cate that the software is now in version 2.) 5. from the device to the controller the data in the 9th to 20th bytes denotes the part number of the device. 'tmp91fw60 _ _ _ ' is sent in ascii code starting from the 9th byte. note: an underscore ('_') indicates a space. 6. from the device to the controller the data in the 21st to 24th bytes is the passwor d comparison start addre ss. f4h, feh, 02h and 00h are sent starting from the 21st byte. 7. from the device to the controller the data in the 25th to 28th bytes is the ram star t address. 00h, 10h, 00h and 00h are sent start- ing from the 25th byte. 8. from the device to the controller the data in the 29th to 32nd bytes is the ram (user area) end address. ffh, 2dh, 00h and 00h are sent starting from the 29th byte. 9. from the device to the controller the data in the 33rd to 36th bytes is the ram en d address. ffh, 2fh, 00 h and 00h are sent start- ing from the 33rd byte. 10. from the device to the controller the data in the 37th to 44th bytes is dummy data. 11. from the device to the controller the data in the 45th and 46th bytes contains the protection status and sector division information of the flash memory. >bit 0 indicates the read protection status. 0: read protection is applied.
page 232 2007-10-15 tmp91fw60 1: read protection is not applied. >bit 1 indicates the write protection status. 0: write protection is applied. 1: write protection is not applied. >bit 2 indicates whether or not the flash memory is divided into sectors. 0: the flash memory is divided into sectors. 1: the flash memory is not divided into sectors. >bits 3 to 15 are sent as ?0?. 12. from the device to the controller the data in the 47th to 50th bytes is the flash memory start address. 00h, 00h, 01h and 00h are sent starting from the 47th byte. 13. from the device to the controller the data in the 51st to 54th bytes is the flash memory end address. ffh, ffh, 02h and 00h are sent starting from the 51st byte. 14. from the device to the controller the data in the 55th and 56th bytes indicates the number of sect ors in the flash memory. 10h and 00h are sent starting from the 55th byte. 15. from the device to the controller the data in the 57th to 65th bytes contains sect or information of the flas h memory. sector informa- tion is comprised of the start address (starting from the flash memory start address), sector size and number of consecutive sectors of the same size. note that the sector size is represented in word units. the data in the 57th to 65th bytes indicates 8 kbytes of sectors (sector 0 to sector 15). for the data to be transferred, see table 14-10. 16. from the device to the controller the data in the 66th byte is checksum data. this is the two's complement of the lower 8-bit value obtained by summing the data in the 5th to 65th bytes by unsigned 8-bit addition (ignoring any overflow). 17. from the controller to the device the data in the 67th byte is the next operation command data.
page 233 2007-10-15 tmp91fw60 14.4.11flash memory chip erase command see table 14-11. 1. the data in the 1st and 2nd bytes is the same as in the case of th e ram transfer command. 2. from the controller to the device the data in the 3rd byte is operation command da ta. the flash memory chip erase command data (40h) is sent here. 3. from the device to the controller the data in the 4th byte is the ack response data to the operation command data in the 3rd byte. the device first checks to see if the data in the 3rd byte contains any erro r. if a receive error is found, the device returns the ack response data fo r communications error (bit 3) x8h and waits for the next operation command data (3rd byte). the uppe r four bits of the ack response data are unde- fined. (they are the upper four bits of the immediately preced ing operation command data.) then, if the data in the 3rd byte corresponds to one of the operation command values given in table 14-7, the device echoes back the received data (ack respons e for normal reception). in this case, 40h is echoed back. if the data in the 3rd byte does not correspond to any operation command, the device returns the ack response data for operation command error (bit 0) x1h and waits for the next operation command data (3rd byte). the uppe r four bits of the ack response data are unde- fined. (they are the upper four bits of the immediately pr eceding operation command data.) 4. from the controller to the device the data in the 5th byte is erase enable command data (54h). 5. from the device to the controller the data in the 6th byte is the ack response data to the erase enable command data in the 5th byte. the device first checks to see if the data in the 5t h byte contains any error. if a receive error is found, the device returns the ack response data fo r communications error (bit 3) x8h and waits for the next operation command data (3rd byte). the uppe r four bits of the ack response data are unde- fined (they are the upper four bits of th e immediately preceding operation command data.) then, if the data in the 5th byte corresponds to the erase enable command data, the device echoes back the received data (ack response for normal reception). in this case, 54h is echoed back and execution jumps to the flash memory chip erase processing routine. if the data in the 5th byte does not correspond to the erase enable command data , the device returns the ack response data for operation command error (bit 0) x1h and waits for the next operation command (3rd byte). the upper four bits of the ack respons e data are undefined. (they are the upper four bits of the immedi- ately preceding operat ion command data.) 6. from the device to the controller the data in the 7th byte indicates whether or not the erase operation has completed successfully. if the erase operation has completed successfully, the de vice returns the end code (4fh). if an erase error has occurred, the device re turns the error code (4ch). 7. from the device to the controller the data in the 8th byte is ack response data. if the erase operation ha s completed successfully, the device returns the ack response for erase comple tion (5dh). if an erase error has occurred, the device returns the ack response for erase error (60h). 8. from the controller to the device the data in the 9th byte is the next operation command data.
page 234 2007-10-15 tmp91fw60 14.4.12flash memory protect set command see table 14-12. 1. the data in the 1st and 2nd bytes is the same as in the case of th e ram transfer command. 2. from the controller to the device the data in the 3rd byte is operation command data. the flash memory protect set command data (60h) is sent here. 3. from the device to the controller the data in the 4th byte is the ack response data to the operation command data in the 3rd byte. the device first checks to see if the data in the 3rd byte contains any erro r. if a receive error is found, the device returns the ack response data fo r communications error (bit 3) x8h and waits for the next operation command data. the upper four bits of the ack response data are undefined. (they are the upper four bits of the im mediately preceding operation command data.) then, if the data in the 3rd byte corresponds to one of the operation command data values given in table 14-7, the device echoes back the received data (ack respons e for normal reception). in this case, 60h is echoed back and execu tion branches to the fl ash memory protect set processing routine. after branching to this routine, the data in the password area is checked. for details, see " 14.4.15 password ". if the data in the 3rd byte does not correspond to any operation command, the device returns the ack response data for operation command error (bit 0) x1h and waits for the next oper- ation command data (3rd byte). the upper four bits of the ack response data are undefined. (they are the upper four bits of the immediately precedin g operation command data.) 4. from the controller to the device the data in the 5th to 16th bytes is password data (12 bytes). the data in the 5th byte is verified against the data at address 02fef4h in the flash me mory and the data in the 6th byte against the data at address 02fef5h. in this manner , the received data is verified cons ecutively against the data at the specified address in the flash memory. the data in th e 16th byte is verified ag ainst the data at address 02feffh in the flash memory. 5. from the controller to the device the data in the 17th byte is checksum data. th e checksum data sent by the controller is the two's complement of the lower 8-bit value obtained by summing the data in 5th to 16th bytes by unsigned 8-bit addition (ignoring any overflow). for details on checksum, see " 14.4.17 how to calculate checksum ". 6. from the device to the controller the data in the 18th byte is the ack response data to the data in the 5th to 17th bytes (ack response to the checksum value). the device first checks to see whether the data in the 5th to 17th bytes contains any error. if a receive error is found, the device returns the ack response data for communications error (bit 3) 68h and waits for the next operation command data (3rd byte). the upper four bits of the ack response data are the upper four bits of the immediately preceding operation command data, so the value of these bits is ?6?. then, the device checks the checksum data in the 17th byte. this check is made to see if the lower 8 bits of the value obtained by summing the data in the 5th to 17th bytes by unsigned 8-bit addition (ignoring any overflow) is 00h. if the value is not 00h, the device returns the ack response data for checksum error (bit 0) 61h and waits for the next operation command data (3rd byte). finally, the device examines the result of password verification. if all the data in the 5th to 16th bytes is not verified correctly, the device return s the ack response data for password error (bit 0) 61h and waits for the next operation command data (3rd byte). if no error is found in the ab ove checks, the device returns the ack response data for normal reception 60h.
page 235 2007-10-15 tmp91fw60 7. from the device to the controller the data in the 19th byte indicates whether or not the protect set opera tion has completed success- fully. if the operation has completed successfully, th e device returns the end code (6fh). if an error has occurred, the device retu rns the error code (6ch). 8. from the device to the controller the data in the 20th byte is ack response data. if the protect set operat ion has completed success- fully, the device returns the ack response data for normal completion (31h). if an error has occurred, the device returns the ack response data for error (34h). 9. from the device to the controller the data in the 21st byte is the next operation command data. 14.4.13ack response data the boot program notifies the controller of its processing status by sending various response data. table 14- 13 to table 14-18 show the ack respons e data returned for each type of r eceived data. the upper four bits of ack response data are a direct refl ection of the upper four bits of th e immediately preceding operation com- mand data. bit 3 indicates a receive error and bit 0 indicates an operat ion command error, checksum error or password error. note: if the desired baud rate cannot be set, the dev ice returns no data and terminates operation. note:the upper four bits are a direct reflection of the upper four bits of the immediately preceding operation com- mand data. table 14-13 ack response data to serial operation mode setting data transfer data meaning 86h the device can communicate in uart mode. (note) table 14-14 ack response data to operation command data transfer data meaning x8h (note) a receive error occurred in the operation command data. x6h (note) terminated receive operation due to protection setting. x1h (note) undefined operation command data was received normally. 10h received the ram transfer command. 20h received the flash memory sum command. 30h received the product information read command. 40h received the flash memory chip erase command. 60h received the flash memory protect set command. table 14-15 ack response data to checksum data for ram transfer command transfer data meaning 18h a receive error occurred. 11h a checksum error or password error occurred. 10h received the correct checksum value.
page 236 2007-10-15 tmp91fw60 note:these codes are returned for reconfirmation of communications. note:these codes are returned for reconfirmation of communications. 14.4.14determining se rial operation mode to communicate in uart mode, the cont roller should transmit the data va lue 86h as the first byte at the desired baud rate. figure 14-7 shows the waveform of this operation. figure 14-7 data for determ ining serial operation mode the boot program receives the first byte (86h) after re set release not as serial communications data. instead, the boot program uses the first byte to determine the ba ud rate. the baud rate is determined by the output peri- ods of tab, tac and tad as shown in figure 14-7 using the procedure shown in figure 14-8. the cpu monitors the level of the receive pin. upon detecting a level change, the cpu captures the timer value to determine the baud rate. table 14-16 ack response data to flash memory chip erase operation transfer data meaning 54h received the erase enable command. 4fh completed erase operation. 4ch an erase error occurred. 5dh (note) reconfirmation of erase operation 60h (note) reconfirmation of erase error table 14-17 ack response data to checksum data for flash memory protect set command transfer data meaning 68h a receive error occurred. 61h a checksum or password error occurred. 60h received the correct checksum value. table 14-18 ack response data to flash memory protect set operation transfer data meaning 6fh completed the protect (read/write) set operation. 6ch a protect (read/write) set error occurred. 31h (note) reconfirmation of protect (read/write) set operation 34h (note) reconfirmation of protect (read/write) set error 7#46
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page 237 2007-10-15 tmp91fw60 figure 14-8 flowchart for serial operation mode receive operation initialize 16-bit timer b0 ( t1 = 8/fc, clear counter) start the prescaler start counting up of 16-bit timer b0 point a stop operation (endless loop) receive pin changed from high to low? yes yes yes start receive pin changed from low to high? capture timer value (tab) by software receive pin changed from high to low? capture timer value (tac) by software yes receive pin changed from low to high? capture timer value (tad) by software stop 16-bit timer b0 tac tad? back up tad value end yes point b point c point d
page 238 2007-10-15 tmp91fw60 14.4.15password when the ram transfer command (1 0h) or the flash memory protect set command (60h) is received as operation command data, password verification is performe d. first, the device echoes back the operation com- mand data (10h to 60h) and checks the data ( 12 bytes) in the password area (addresses 02fef4h to 02feffh). then, the device verifies the password data received in the 5th to 16th bytes against the data in the password area as shown in table 14-19. unless all the 12 bytes are verified co rrectly, a password error will occur. a password error will also occur if all the 12 bytes of password data contain the same value. only exception is when all the 12 bytes are ?ffh? and verified corr ectly and the reset vector area (addresses 02ff00h to 02ff02h) is all ?ffh?. in this cas e, a blank device will be assumed and no password error will occur. if a password error has occurred, the device returns th e ack response data for password error in the 18th byte. table 14-19 password verification table receive data data to be verified against 5th byte data at address 02fef4h 6th byte data at address 02fef5h 7th byte data at address 02fef6h 8th byte data at address 02fef7h 9th byte data at address 02fef8h 10th byte data at address 02fef9h 11th byte data at address 02fefah 12th byte data at address 02fefbh 13th byte data at address 02fefch 14th byte data at address 02fefdh 15th byte data at address 02fefeh 16th byte data at address 02feffh example of data that cannot be specified as a password for blank products (note) the password of a blank product must be all ?ffh? (ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh). note:a blank product is a product in which all the bytes in the password area (addresses 02fef4h to 02feffh) and the reset vector area (addresses 02ff00h to 02ff02h) are ?ffh?. for programmed products the same 12 consecutive bytes cannot be specified as a password. the table below shows password error examples. programmed product 1 2 3 4 5 6 7 8 9 10 11 12 note error example 1 ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh ffh all"ff" error example 2 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h all"00" error example 3 5ah 5ah 5ah 5ah 5ah 5ah 5ah 5ah 5ah 5ah 5ah 5ah all"5a"
page 239 2007-10-15 tmp91fw60 14.4.16how to calculate sum sum is calculated by summing the values of all data read from the flash memory by unsigned 8-bit addition and is returned as a word (16-bit) value. the resulting sum value is sent to the controller in order of upper 8 bits and lower 8 bits. all the 128 kbytes of data in the flash memory are include d in the calculation of sum. when the flash memory sum command is ex ecuted, sum is calculated in this way. 14.4.17how to calculate checksum checksum is calculated by taking the two's complement of the lower 8-bit value obtained by summing the values of received data by unsign ed 8-bit addition (ignoring any over flow). when the flash memory sum command or the product info rmation read command is executed, checksum is calculated in this way. the controller should also use this checksum calculation method for sending checksum values. example: calculating checksum for the flash memory sum command when the upper 8-bit data of sum is e5h and the lower 8-bit data is f6h, checksum is calculated as shown below. first, the upper 8 bits and lower 8 bits of the sum value are added by unsigned operation. e5h+f6h = 1dbh then, the two's complement of the lower 8 bits of this result is obtained as shown below. the resulting checksum value (25h) is sent to the controller. 0-dbh = 25h 14.5 user boot mode (in single chip mode) user boot mode, which is a sub mode of single chip mode, enables a user-created flash memory program/erase routine to be used. to do so, the operation mode of single chip mode must be changed from normal mode for exe- cuting a user application program to user boot mode for programming/erasing the flash memory. for example, the reset processing rou tine of a user application program may include a routine fo r selecting normal mode or user boot mode upon entering single chip mo de. any mode-selecting condition may be set using the device's i/o to suit the user system. to program/erase the flash memory in user boot mode, a program/erase routine must be incorporated in the user application program in advance. since the processor cannot read data from th e internal flash memory while it is being programmed or erased, the program/erase routine mu st be executed from the outside of the flash memory. while the flash memory is being programmed/erased in user boot mode, interrupts must be disabled. the pages that follow explain the procedure for progra mming the flash memory usi ng two example cases. in one case the program/erase routine is stored in the internal flash memory (1-a); in the other the program/erase routine is transferred from an ex ternal source (1-b).  #*  $*  %*  &*  9jgp57/kuecnewncvgfhtqovjghqwtfcvcgpvtkgu ujqypvqvjgnghvvjgtguwnvkucuhqnnqyu  #* $* %* &*'#*      57/wrrgtdkvu*    57/nqygtdkvu'#*   6jwuvjg57/xcnwgkuugpvvqvjgeqpvtqnngtkp qtfgtqh*cpf'#*
page 240 2007-10-15 tmp91fw60 14.5.1 (1-a) program/era se procedure example 1 when the program/erase routine is stored in the internal flash memory (step-1)environment setup first, the condition (e.g. pin status) for entering user boot mode must be set and the i/o bus for trans- ferring data must be determined. then, the device's peripheral circuitry must be designed and a corre- sponding program must be written. before mounting the device on the board, it is necessary to write the following four routines into one of the sectors in the flash memory. (a)mode select routine: selects normal mode or user boot mode. (b)program/erase routine: loads program/erase data from an external source and programs/erases the flash memory. (c)copy routine 1: copies routines (a) to (d) into the internal ram or external memory. (d)copy routine 2: copies routines (a) to (d) from the internal ram or external memory into the flash memory. note:the above (d) is a routine for reconstructing the progr am/erase routine on the flash memory. if the entire flash memory is always programmed and the program/erase routine is included in the new user application pro- gram, this copy routine is not needed. 
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page 241 2007-10-15 tmp91fw60 (step-2) entering user boot mode (using the reset processing) after reset release, the reset pro cessing program determines whether or not the device should enter user boot mode. if the condition for entering user boot mode is true, user boot mode is entered to program/ erase the flash memory. (step-3) copying the program/erase routine after the device has entered user boot mode, the copy routine 1 (c) copies the routines (a) to (d) into the internal ram or external memory (the rout ines are copied into the internal ram here.)   4#/  =?   
   
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page 242 2007-10-15 tmp91fw60 (step-4) erasing the flash memory by the program/erase routine control jumps to the program/erase routine in the ram and the old user progr am area is erased (sector erase or chip erase). (in this case, the flash memory erase comm and is issued from the ram.) note: if data is erased on a sector basis and the routines (a) to (d) are left in the flash memory, only the program/ erase routine (b) need be copied into the ram. (step-5) restoring the user boot program in the flash memory the copy routine 2 (d) in the ram copies the routines (a) to (d) into the flash memory. note: if data is erased on a sector basis and the routines (a) to (d) are left in the flash memory, step 5 is not needed.   4#/ 
    
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page 243 2007-10-15 tmp91fw60 (step-6) writing the new user application program to the flash memory the program/erase routine in the ra m is executed to load the new us er application program from the controller into the erased area of the flash memory. (step-7) executing the new user application program the reset input pin is driven low (?0?) to reset the device. the mode setting condition is set for nor- mal mode. after reset release, the device will st art executing the new us er application program.   4#/  =?  
    
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page 244 2007-10-15 tmp91fw60 14.5.2 (1-b) program/era se procedure example 2 in this example, only the boot program (minimum requirement) is stored in the flash memory and other nec- essary routines are supp lied from the controller. (step-1)environment setup first, the condition (e.g. pin status) for entering user boot mode must be set and the i/o bus for trans- ferring data must be determined. then, the device's peripheral circuitry must be designed and a corre- sponding program must be written. before mounting the device on the board, it is necessary to write the following two routines into one on the sectors in the flash memory. (a)mode select routine: selects normal mode or user boot mode. (b)transfer routine: loads the program/erase routin e from an ex ternal source. the following routines are pr epared on the controller. (c)program/erase routine: programs/erases the flash memory. (d)copy routine 1: copies routines (a) and (b) into th e internal ram or external memory. (e)copy routine 2: copies routines (a) and (b) from the internal ram or external memory into the flash memory. 
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page 245 2007-10-15 tmp91fw60 (step-2) entering user boot mode (using the reset processing) the following explanation assumes that these routines are incorporated in the reset processing program. after reset release, the reset pro cessing program first determines whether or not the device should enter user boot mode. if the condition for entering user boot mode is true, user boot mode is entered to pro- gram/erase the flash memory. (step-3) copying the program/eras e routine to the internal ram after the device has entered user boot mode, the tran sfer routine (b) transfers the routines (c) to (e) from the controller to the internal ram (or external memory). (the routines are copied into the internal ram here.) 

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page 246 2007-10-15 tmp91fw60 (step-4) executing the copy ro utine 1 in the internal ram control jumps to the internal ram and the copy rout ine 1 (d) copies the routin es (a) and (b) into the internal ram. (step-5) erasing the flash memory by the program/erase routine the program/erase routine (c) eras es the old user program area. 
 
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page 247 2007-10-15 tmp91fw60 (step-6) restoring the user boot program in the flash memory the copy routine (e) copies the ro utines (a) and (b) from the internal ram into the flash memory. (step-7) writing the new user application program to the flash memory the program/erase routine (c) in the ram is execute d to load the new user application program from the controller into the eras ed area of the flash memory. 
 
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page 248 2007-10-15 tmp91fw60 (step-8) executing the new user application program the reset input pin is driven low (?0?) to reset the device. the mode setting condition is set for nor- mal mode. after reset release, the device will st art executing the new us er application program. 
 
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page 249 2007-10-15 tmp91fw60 14.6 flash memory command sequences the operation of the flash memory is comprised of six commands, as shown in table 14-20. addresses specified in each command sequence must be in an area where the flash memory is mapped. for details, see table 14-3. note 1: pa = program word address, pd = program word data set the address and data to be programmed. even-numbered addresses should be specified here. note 2: sa = sector erase address, each sector erase range is selected by address a23 to a13. note 3: when apply read protect and write protect, be sure to program the data of 00h. note: d15 to d8 and d5 to d0 are ?don't care?. table 14-20 command sequences command 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle sequence addr. data addr. data addr. data addr. data addr. data addr. data 1 single word program aaah aah 554h 55h aaah a0h pa (note1) pd (note1) 2 sector erase (8kb erase) aaah aah 554h 55h aaah 80h aaah aah 554h 55h sa (note2) 30h 3 chip erase (all erase) aaah aah 554h 55h aaah 80h aaah aah 554h 55h aaah 10h 4 product id entry aaah aah 554h 55h aaah 90h 5 product id exit xxh f0h product id exit aaah aah 554h 55h aaah f0h 6 read protect set aaah aah 554h 55h aaah a5h 77eh f0h (note3) write protect set aaah aah 554h 55h aaah a5h 77eh 0fh (note3) table 14-21 hardware sequence flags status d7 d6 during auto opera- tion single word program d7 toggle sector erase/chip erase 0 toggle read protect set/write protect set cannot be used toggle
page 250 2007-10-15 tmp91fw60 14.6.1 single word program the single word program command sequence programs the flash memory on a word basis. the address and data to be programmed are specified in the 4th bus write cycle. it takes a maximum of 60 us to program a sin- gle word. another command sequence cannot be executed until the write operation has completed. this can be checked by reading the same address in the flash memory repeatedly until the same data is read consecutively. while a write operation is in progress, bit 6 of data is t oggled each time it is read. note:to rewrite data to flash memory addresses at which dat a (including ffffh) is already written, make sure to erase the existing data by ?sector erase? or ?chip erase? before rewriting data. 14.6.2 sector erase (8-kbyte erase) the sector erase command sequence erases 8 kbytes of data in the flash memory at a time. the flash mem- ory address range to be erased is specified in the 6th bus write cycle. for the addr ess range of each sector, see table 14-3. this command sequence cannot be used in programmer mode. it takes a maximum of 75 ms to erase 8 kbytes. another command sequence cannot be executed until the erase operation has completed. this can be checked by reading the same address in the flash memory repeat- edly until the same data is read consecutively. while a erase operation is in progress, bit 6 of data is toggled each time it is read. 14.6.3 chip erase (all erase) the chip erase command sequence erases the entire area of the flash memory. it takes a maximum of 300 ms to erase the entire flash memory. another command sequence cannot be exe- cuted until the erase operation has completed. this can be checked by reading the same address in the flash memory repeatedly until the same data is read consecu tively. while a erase operati on is in progress, bit 6 of data is toggled each time it is read. erase operations clear data to ffh. 14.6.4 product id entry when the product id entry command is executed, product id mode is entered. in this mode, the vendor id, flash macro id, flash size id, and read/write protect st atus can be read from the flash memory. in product id mode, the data in the flash memory cannot be read. 14.6.5 product id exit this command sequence is used to exit product id mode.
page 251 2007-10-15 tmp91fw60 14.6.6 read protect set the read protect set command sequence applies read protection on the flash memo ry. when read protection is applied, the flash memory cannot be read in pr ogrammer mode and the ram transfer command cannot be executed in single boot mode. to cancel read protection, it is n ecessary to execute the chip erase co mmand sequence. to check whether or not read protection is applied, read xxx77eh in product id mode. it takes a maximum of 60 us to set read pro- tection on the flash memory. another command sequence cannot be executed until th e read protection setting has completed. this can be checked by reading the same address in the fl ash memory repeatedly until the same data can be read consecutively. while a read protect oper ation is in progress, bit 6 of data is toggled each time it is read. 14.6.7 write protect set the write protect set command sequence applies write protection on the flash memory. when write protec- tion is applied, the flash memory cannot be written to in programmer mode and the ram transfer command cannot be executed in single boot mode. to cancel write protection, it is ne cessary to execute the chip erase command sequence. to check whether or not write protection is applied, read xxx77eh in product id mode. it takes a maximum of 60 us to set write protection. another command sequence cannot be executed until the write protection setting has completed. this can be checked by reading the same address in th e flash memory repeatedly until the same data can be read consecutively. while a write protect operation is in progress, bit 6 of data is togg led each time it is read. 14.6.8 hardware sequence flags the following hardware sequence flags are available to check the auto oper ation execution status of the flash memory. 1. data polling (d7) when data is written to the flash memory, d7 ou tputs the complement of its programmed data until the write operation has completed. after the writ e operation has completed, d7 outputs the proper cell data. by reading d7, therefor e, the operation status can be checked. while the sector erase or chip erase command sequence is being executed, d7 outputs ?0?. after the command sequence is completed, d7 outputs ?1? (cell data). then, the data written to all the bits can be read after waiting for 1 us. when read/write protection is applied, the data polling function cannot be used. instead, use the toggle bit (d6) to check the operation status. 2. toggle bit (d6) when the flash memory program, s ector erase, chip erase, write pr otect set, or read protect set command sequence is executed, bit 6 (d6) of the da ta read by read operat ions outputs ?0? and ?1? alternately each time it is read until the processing of the executed command sequence has com- pleted. the toggle bit (d6) thus provides a software means of checking whether or not the processing of each command sequence has comple ted. normally, the same addre ss in the flash memory is read repeatedly until the same data is read successively. the initial read of the to ggle bit always returns ?1?. note:the flash memory incorporated in the tmp91fw60 does not have an exceed-time-limit bit (d5). it is therefore necessary to set the data polling time limit and toggle bi t polling time limit so that polling can be stopped if the time limit is exceeded.
page 252 2007-10-15 tmp91fw60 14.6.9 data read data is read from the flash memory in byte units or word units. it is not nece ssary to execute a command sequence to read data from the flash memory. 14.6.10programming the flash me mory by the internal cpu the internal cpu programs the flash memory by using the command sequences and hardware sequence flags described above. however, since the flash memory canno t be read during auto op eration mode, the program/ erase routine must be executed outside of the flash memory. the cpu can program the flash memory either by using single boot mode or by using a user-created proto- col in single chip mode (user boot). 1. single boot: the microcontroller is started up in single boot mode to program the flash memory by the internal boot rom program. in this mode, the internal boot rom is mapped to an area including the interrupt vector table, in which the boot rom program is ex ecuted. the flash memory is mapped to an address area different from the boot rom area. the boot ro m program loads data into the flash memory by serial transfer. in single boot mode, interrupts must be disabled including non-maskable interrupts (nmi , etc.). for details, see " 14.4 single boot mode " 2. user boot: in this method, the flash memory is programme d by executing a user-cr eated routine in single chip mode (normal operation mode). in this mode, the user-created program/ erase routine must also be executed outside of the flash memory. it is also necessary to disable interrupts including non- maskable interrupts. the user should prepare a flash memory program/e rase routine (including routines for loading write data and writing the loaded data into the flas h memory). in the main program, normal operation is switched to flash memory pr ogramming operation to execute th e flash memory program/erase rou- tine outside of the flash memory area. for example, the flash me mory program/erase routine may be transferred from the flash memory to the internal ram and executed there or it may be prepared and executed in external memory. for details, see " 14.5 user boot mode (in single chip mode) ".
page 253 2007-10-15 tmp91fw60 flowcharts: flash memory access by the internal cpu single word program 2tqitcoeqoocpfugswgpeg (see the flowchart below) 5vctv 6qiingdkv
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page 254 2007-10-15 tmp91fw60 chip erase/sector erase  %jkr'tcug%qoocpf5gswgpeg
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page 255 2007-10-15 tmp91fw60 read/write protect set protect set command sequence (address/data) xxxaaah/aah xxx554h/55h xxxaaah/a5h set read protect xxx77eh/f0h set write protect xxx77eh/0fh set both read protect and write protect xxx77eh/00h protect set command sequence (see the flowchart below) start toggle bit (d6) protect set end abnormal end yes timeout (60 s) product id entry read data matched p ro g ram data? product id exit byte read (d7 to d0) addr. = xxx77eh no toggle bit (d6) protect set command sequence (see the flowchart below) product id entry product id exit
page 256 2007-10-15 tmp91fw60 data polling (d7) toggle bit (d6) note:hardware sequence flags are read from the flash memory in byte units or word units. va:in single word program, va denotes the address to be programmed. in sector erase, va denotes any address in the selected sector. in chip erase, va denotes an y address in the flash memory. in read protect set, va denotes the protect set address (xx77eh). in write protect set, va denotes the protect set address (xx77eh).  $[vgtgcf
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page 258 2007-10-15 tmp91fw60 (example: program to be lo aded and executed in ram) erase the flash memory (chip erase) a nd then write 0706h to address fe0000h. ;#### flash memory ch ip erase processing #### ld xix, 0xfe0000 ; set start address chiperase: ld (0xfe0aaa), 0xaa ;1st bus write cycle ld (0xfe0554), 0x55 ;2nd bus write cycle ld (0xfe0aaa), 0x80 ;3rd bus write cycle ld (0xfe0aaa), 0xaa ;4th bus write cycle ld (0xfe0554), 0x55 ;5th bus write cycle ld (0xfe0aaa), 0x10 ;6th bus write cycle cal togglechk ; check toggle bit chiperase _ loop: ld wa, (xix+) ; read data from flash memory cp wa, 0xffff ; blank data? j ne,chiperase _ err ; if not blank data, jump to error processing cp xix, 0xffffff ; end address (0xffffff)? j ult,chiperase _ loop ; check entire memory area and then end loop processing ;#### flash memory program processing #### ld xix, 0xfe0000 ; set program address ld wa, 0x0706 ; set program data program: ld (0xfe0aaa), 0xaa ;1st bus write cycle ld (0xfe0554), 0x55 ;2nd bus write cycle ld (0xfe0aaa), 0xa0 ;3rd bus write cycle ld (xix), wa ;4th bus write cycle cal togglechk ; check toggle bit ld bc, (xix) ; read data from flash memory cp wa, bc j ne, program _ err ; if programmed data cannot be read, error is determined ld bc, (xix) ; read data from flash memory cp wa, bc j ne, program _ err ; if programmed data cannot be read, error is determined program _ end: j program _ end ; program operation end
page 259 2007-10-15 tmp91fw60 ;#### toggle bit (d6) check processing #### togglechk: ld l, (xix) and l, 0y01000000 ; check toggle bit (d6) ld h, l ; save first toggle bit data togglechk1: ld l, (xix) and l, 0y01000000 ; check toggle bit (d6) cp l, h ; toggle bit = toggled? j z, togglechk2 ; if not toggled, end processing ld h, l ; save current toggle bit state j togglechk1 ; recheck toggle bit togglechk2: ret ;#### error processing #### chiperase _ err: j chiperase _ err ; chip erase error program _ err: j program _ err ; program error
page 260 2007-10-15 tmp91fw60 (example: program to be lo aded and executed in ram) erase data at addresses ff0000h to ff1fffh (sector erase) and then write 0706h to address ff0000h. ;#### flash memory sector erase processing #### ld xix, 0xff0000 ; set start address sectorerase: ld (0xfe0aaa), 0xaa ;1st bus write cycle ld (0xfe0554), 0x55 ;2nd bus write cycle ld (0xfe0aaa), 0x80 ;3rd bus write cycle ld (0xfe0aaa), 0xaa ;4th bus write cycle ld (0xfe0554), 0x55 ;5th bus write cycle ld (xix), 0x30 ;6th bus write cycle cal togglechk ; check toggle bit sectorerase _ loop: ld wa, (xix+) ; read data from flash memory cp wa, 0xffff ; blank data? j ne,sectorerase _ err ; if not blank data, jump to error processing cp xix, 0xff1fff ; end address (0xff1fff)? j ult,sectorerase _ loop ; check erased sector area and then end loop processing ;#### flash memory program processing #### ld xix, 0xff0000 ; set program address ld wa, 0x0706 ; set program data program: ld (0xfe0aaa), 0xaa ;1st bus write cycle ld (0xfe0554), 0x55 ;2nd bus write cycle ld (0xfe0aaa), 0xa0 ;3rd bus write cycle ld (xix), wa ;4th bus write cycle cal togglechk ; check toggle bit ld bc, (xix) ; read data from flash memory cp wa, bc j ne, program _ err ; if programmed data cannot be read, error is determined ld bc, (xix) ; read data from flash memory cp wa, bc j ne, program _ err ; if programmed data cannot be read, error is determined program _ end: j program _ end ; program operation end
page 261 2007-10-15 tmp91fw60 ;#### toggle bit (d6) check processing #### togglechk: ld l, (xix) and l, 0y01000000 ; check toggle bit (d6) ld h, l ; save first toggle bit data togglechk1: ld l, (xix) and l, 0y01000000 ; check toggle bit (d6) cp l, h ; toggle bit = toggled? j z, togglechk2 ; if not toggled, end processing ld h, l ; save current toggle bit state j togglechk1 ; recheck toggle bit togglechk2: ret ;#### error processing #### sectorerase _ err: j sectorerase _ err ; sector erase error program _ err: j program _ err ; program error
page 262 2007-10-15 tmp91fw60 (example: program to be lo aded and executed in ram) set read protection and write protection on the flash memory. ;#### flash memory protect set processing #### ld xix, 0xfe077e ; set protect address protect: ld (0xfe0aaa), 0xaa ;1st bus write cycle ld (0xfe0554), 0x55 ;2nd bus write cycle ld (0xfe0aaa), 0xa5 ;3rd bus write cycle ld (xix), 0x00 ;4th bus write cycle cal togglechk ; check toggle bit cal pid _ entry ; ld a, (xix) ; read protected address lcal pid _ exit ; cp a, 0x00 ;(0xfe077e)=0x00? j ne, protect _ err ; protected? protect _ end: j protect _ end ; protect set operation completed protect _ err: j protect _ err ; protect set error ;#### product id entry processing #### pid _ entry: ld (0xfe0aaa), 0xaa ;1st bus write cycle ld (0xfe0554), 0x55 ;2nd bus write cycle ld (0xfe0aaa), 0x90 ;3rd bus write cycle ; --- wait for 300 nsec or longer (execute nop instruction [200nsec/@f fph =20mhz] two times) --- nop nop ; wait for 400 nsec ret ;#### product id exit processing #### pid _ exit: ld (0xfe0000), 0xf0 ;1st bus write cycle ; --- wait for 300 nsec or longer (execute nop instruction [200nsec/@f fph =20mhz] two times) --- nop nop ; wait for 400 nsec ret
page 263 2007-10-15 tmp91fw60 (example: program to be lo aded and executed in ram) read data from address fe0000h. ;#### toggle bit (d6) check processing #### togglechk: ld l, (xix) and l, 0y01000000 ; check toggle bit (d6) ld h, l ; save first toggle bit data togglechk1: ld l, (xix) and l, 0y01000000 ; check toggle bit (d6) cp l, h ; toggle bit = toggled? j z, togglechk2 ; if not toggled, end processing ld h, l ; save current toggle bit state j togglechk1 ; recheck toggle bit togglechk2: ret ;#### flash memory read processing #### read: ld wa, (0xfe0000) ; read data from flash memory
page 264 2007-10-15 tmp91fw60 15. electrical characteristics 15.1 absolute maximum ratings note: absolute maximum ratings are limiti ng values of operating and environmental conditions which should not be exceeded under the worst possible conditions. the equipment manufacturer should design so that no absolute maximum rating value is exceeded. exposure to conditions beyond those listed above may cause per manent damage to the device or affect device reliability, which could increase potential risks of personal injury due to ic blowup and/or burning. parameter symbol pin name rating unit supply voltage v cc ? 0.5 to 6.0 v input voltage v in ? 0.5 to v cc + 0.5 v output current (per pin) i ol1 p5, p6, p96, p97 2 ma output current (per pin) i ol2 p0, p1, p2, p3, p4, p7, p8, p90-p95, pa, pb, pz 5ma output current (per pin) i oh1 p5, p6, p96, p97 ? 2ma output current (per pin) i oh2 p0, p1, p2, p3, p4, p7, p8, p90-p95, pa, pb, pz ? 5ma output current (total) i ol 80 ma output current (total) i oh ? 80 ma power dissipation (t opr = 85 c) pd 600 mw soldering temperature (10 s) t solder 260 c storage temperature t stg ? 65 to 150 c operating temperature t opr ? 40 to 85 c solderability of lead free products test parameter test condition note solderability use of sn-37pb solder bath solder bath temperature 230 c, dipping time 5 [s] the number of times one, use of r-type flux pass: solderability rate until forming 95% use of sn-3.0ag-0.5 cu solder bath solder bath temperature 245 c, dipping time 5 [s] the number of times one, use of r-type flux (use of lead free)
page 265 2007-10-15 tmp91fw60 15.2 dc electrical characteristics note 1: typical values show those at t opr = 25 c and vdd = 5 v. note 2: i cc measurement conditions (normal, sl ow): all functions are operational; ou tput pins are open and input pins are level fixed. data and address bus cl = 30 pf loaded. note 3: when a program is executing in the flash memory or w hen data is being read from the flash memory, the flash memory operates in an intermittent manner, causing peak curr ents in the operation current, as shown in figure 15-1. in this case, the supply current i cc (in normal and slow modes) is defined as the sum of the average peak current and mcu current. parameter symbol condition min typ. max unit power supply voltage (av cc = dv cc ) (av ss = dv ss = 0v) v cc fc = 4 to 20 mhz fs = 30 to 34 khz 4.5 5.5 v for erase/program operations of flash memory (av cc = dv cc ) (av ss = dv ss = 0v) fc = 4 to 20 mhz t opr = -10 to 4 0 c 4.75 5.25 low-level input volt- age p00 to p17(ad0 to ad15) v il v cc = 4.5 to 5.5 v ? 0.3 0.8 v p20 to p27, pz0 to pz3 v il1 0.3 v cc reset , nmi , p30 to pb3 v il2 0.25 v cc am0, am1 v il3 0.3 x1 v il4 0.2 v cc high-level input volt- age p00 to p17(ad0 to ad15) v ih v cc = 4.5 to 5.5 v 2.2 v cc + 0.3 v p20 to p27, pz0 to pz3 v ih1 0.7 v cc reset , nmi , p30 to pb3 v ih2 0.75 v cc am0, am1 v ih3 v cc ? 0.3 x1 v ih4 0.8 v cc low-level output voltage v ol i ol = 1.6 ma (v cc = 4.5 to 5.5 v) 0.45 v high-level output voltage v oh i oh = ? 400 a (v cc = 4.5 to 5.5 v) 4.2 v i oh = ? 1.6 ma (v cc = 4.5 to 5.5 v) 2.4 input leakage current i li 0.0 v in v cc 0.02 5 a output leakage current i lo 0.2 v in v cc ? 0.2 0.05 10 power down voltage (while ram is being backed up in stop mode) v stop v il2 = 0.2 v cc v ih2 = 0.8 v cc 2.0 5.5 v reset pull-up resistor r rst v cc = 4.5 to 5.5 v 50 230 k pin capacitance c io fc = 1 mhz 10 pf schmitt width reset , nmi , int0 v th v cc = 4.5 to 5.5 v 0.4 1.0 v programmable pull-up resistor rkh v cc = 4.5 to 5.5 v 50 230 k normal (note 2) i cc v cc = 4.5 to 5.5 v fc = 20 mhz 25 35 ma idle2 815 idle1 3.5 8 slow (note 2) v cc = 4.5 to 5.5 v fs = 32.768 khz 80 100 a stop t opr 50 c v cc = 4.5 to 5.5 v 0.5 10 a t opr 70 c 25 t opr 85 c 50 peak current for intermittent operation (note 3,4) i ddp-p v dd = 5.5 v ? 20 ? ma
page 266 2007-10-15 tmp91fw60 note 4: when designing the power supply, make sure that p eak currents can be supplied. in slow1 mode, the difference between the peak current and the average current becomes large. figure 15-1 intermittent operation of flash memory n program coutner (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu current
page 267 2007-10-15 tmp91fw60 15.3 ac characteristics 15.3.1 v cc = 5.0 v 10% ac measuring conditions ? output level:high 0.7v cc /low 0.3v cc , cl = 50 pf ? input level:high 0.9v cc /low 0.1v cc note:symbol ?x? in the above table means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting or the selection of high-/low-oscillator fre- quency. no. parameter symbol variable f fph = 20mhz unit min max min max 1 f fph period ( = x) t fph 50.0 31250 50.0 ns 2 a0 to a15 valid ale falling t al 0.5 x ? 15 10 ns 3 ale falling a0 to a15 hold t la 0.5 x ? 15 10 ns 4 ale high pulse width t ll x ? 20 30 ns 5 ale falling rd / wr falling t lc 0.5 x ? 20 5 ns 6 rd rising ale rising t clr 0.5 x ? 15 10 ns 7 wr rising ale rising t clw x ? 15 35 ns 8 a0 to a15 valid rd / wr falling t acl x ? 25 25 ns 9 a0 to a21 valid rd / wr falling t ach 1.5 x ? 50 25 ns 10 rd rising a0 to a21 hold t car 0.5 x ? 20 5 ns 11 wr rising a0 to a21 hold t caw x ? 20 30 ns 12 a0 to a15 valid d0 to d15 input t adl 3.0 x ? 45 105 ns 13 a0 to a21 valid d0 to d15 input t adh 3.5 x ? 35 140 ns 14 rd falling d0 to d15 input t rd 2.0 x ? 40 60 ns 15 rd low pulse width t rr 2.0x ? 20 80 ns 16 rd rising d0 to d15 hold t hr 00ns 17 rd rising a0 to a15 output t rae x ? 15 35 ns 18 wr low pulse width t ww 1.5x ? 20 55 ns 19 d0 to d15 valid wr rising t dw 1.5x ? 50 25 ns 20 wr rising d0 to d15 hold t wd x ? 15 35 ns 21 a0 to a23 valid to wait input ((1 + n) wait mode) t awh 3.5x ? 90 85 ns 22 a0 to a15 valid to wait input ((1 + n) wait mode) t awl 3.0x ? 80 70 ns 23 wait hold after rd /wr asserted((1 + n) wait mode) t cw 2.0x + 0 100 ns 24 a0 to a21 valid port input t aph 3.5x ? 120 55 ns 25 a0 to a21 valid port hold t aph2 3.5x 175 ns 26 a0 to a21 valid port valid t ap 3.5x + 100 275 ns
page 268 2007-10-15 tmp91fw60 15.3.2 read cycle note: since the cpu accesses the internal area to read data from a port, the control signals of external pins such as rd and cs are not enabled. therefore, the above waveform diagram should be regarded as depicting internal operation. please also note that the timing and ac characterist ics of port input/output shown above are typi cal representation. for details, contact your local toshiba sales representative. figure 15-2 read cycle f fph a0~a23 cs0~cs3 r/w port input ad0~ad15 ale rd wait t fph t hr t car t aph t awh t awl t rae t cw t aph2 d0 ~d 15 a0 ~a 15 t al t ll t la t lc t rd t rr t clr t adh t adl t ach t acl
page 269 2007-10-15 tmp91fw60 15.3.3 write cycle note: since the cpu accesses the internal area to write dat a to a port, the control signals of external pins such as wa and cs are not enabled. therefore, the waveform diagram should be regarded as depicting internal operation. please also note that the timing and ac characteristics of port input/output shown above ar e typical representation. for details, contact your local toshiba sales representative. figure 15-3 write cycle f fph a0~a23 cs0~cs3 r/w port output h ) ad0~ad15 wait t wd t dw t caw t ww d0 ~d 15 wr, hwr a0 ~a 15 t ap ale t clw
page 270 2007-10-15 tmp91fw60 15.4 ad conversi on characteristics note 1: 1lsb = (v refh ? a vss )/1024 [v] note 2: the operation above is guaranteed for f fph 4 mhz. note 3: the value for i cc includes the current which flows through the a vcc pin. av cc = v cc , av ss = v ss parameter symbol variable min typ. max unit analog reference voltage ( + ) v refh v cc = 4.5 to 5.5 v v cc ? 1.5 v v cc v cc v analog reference voltage ( ? ) a vss v ss v ss v ss + 0.2 v v analog input voltage range v ain a vss v refh v analog current for analog reference voltage = 1 i ref (a vss = 0 v) 1.44 2.00 ma = 0 0.02 5.0 a error (not including quantizing errors) ? 1.0 4.0 lsb
page 271 2007-10-15 tmp91fw60 15.5 serial channel timi ng (i/o internal mode) 15.5.1 sclk input mode note: symbol ?x? in the above tabl e means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting or the selection of high-/low-oscillator frequency. 15.5.2 sclk output mode note 1: *: sclk rising/falling edge:the rising edge is used in sclk rising mode. the falling edge is used in sclk falling mode. note 2: 20 mhz and 16 mhz values are calculated from t scy = 16x case. note 3: symbol ?x? in the above table means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting or the se lection of high-/low-oscillator frequency. parameter symbol variable 20 mhz 16 mhz unit min max min max min max sclk period t scy 16x 800 1000 ns output data sclk rising/falling edge* t oss t scy /2 ? 4x ? 85 (v cc = 5v 10%) 115 165 ns sclk rising/falling edge* output data hold t ohs t scy /2 + 2x + 0 500 625 ns sclk rising/falling edge* input data hold t hsr 3x + 10 160 198 ns sclk rising/falling edge* valid data input* t srd t scy ? 0 800 1000 ns valid data input sclk rising/falling edge* t rds 000ns parameter symbol variable 20 mhz 16 mhz unit min max min max min max sclk period t scy 16x 8192x 0.8 410 1.0 512 s output data sclk rising/falling edge* t oss t scy /2 ? 40 360 460 ns sclk rising/falling edge* output data hold t ohs t scy /2 ? 40 360 460 ns sclk rising/falling edge* input data hold t hsr 000ns sclk rising/falling edge* valid data input t srd t scy ? 1x ? 90 660 847 ns valid data input sclk rising/falling edge* t rds 1x + 90 140 153 ns 0123 0123 valid valid valid valid output data txd input data rxd sclk (rising edge) sclk (falling edge) t oss t srd t scy t rds t hsr t ohs
page 272 2007-10-15 tmp91fw60 15.6 event counter ta0in, ta4in, tb0in0, tb0in1, tb1in0,tb1in1, tb2in0,tb2in1, tb3in0,tb3in1, tb4in0,tb4in1 note: symbol ?x? in the above tabl e means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting or the selection of high-/low-oscillator frequency. parameter symbol variable 20 mhz 16 mhz unit min max min max min max clock period t vck 8x + 100 500 600 ns clock low-level width t vckl 4x + 40 240 290 ns clock high-level width t vckh 4x + 40 240 290 ns
page 273 2007-10-15 tmp91fw60 15.7 interrupt and capture 15.7.1 nmi , int0 interrupts note: symbol ?x? in the above tabl e means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting or the selection of high-/low-oscillator frequency. 15.7.2 int1 to int10 interrupts, capture int1 to int10 input pulse width depend on the syst em clock selection and cloc k selection for prescaler. below table show pulse width of each operation clock. note 1: ?xc? shows period of clock fc in high frequency oscillator. note 2: symbol ?x? in the above table means the period of clock ?f fph ?, it?s half period of the system clock ?f sys ? for cpu core. the period of f fph depends on the clock gear setting or the se lection of high-/low-oscillator frequency. parameter symbol variable 20 mhz 16 mhz unit min max min max min max nmi, int0 low-level width t intal 4x + 40 240 290 ns nmi , int0 high-level width t intah 4x + 40 240 290 ns system clock selection syscr1 clock selection for prescaler syscr0 t intbl (int1 to int10 low level pulse width) t intbh (int1 to int10 high level pulse width) unit variable f fph = 20mhz variable f fph = 20 mhz min min min min 0 (fc) 0 (f fph ) 8x + 100 500 8x + 100 500 ns 1 (fc/16) 128xc + 0.1 6.5 128xc + 0.1 6.5 us 1 (fc) 0 (f fph ) 8x + 0.1 244.3 8x + 0.1 244.3
page 274 2007-10-15 tmp91fw60 15.8 scout pin ac characteristics note: t = period of scout measuring conditions output level: high = 0.7 v cc , low = 0.3 v cc , cl = 10 pf 15.9 flash characteristics 15.9.1 write/retenti on characteristics parameter symbol variable 20 mhz 16 mhz condition unit min max min max min max low-level width t sch 0.5t ? 15 10 16 v cc 4.5v ns high-level width t scl 0.5t ? 15 10 16 v cc 4.5v ns (v ss = 0 v) parameter condition min typ. max. unit number of guaranteed writes to flash memory v ss = 0 v fc = 4 to 20 mhz t opr = ? 10 to 40 c ?? 100 times t sch t scl scout
page 275 2007-10-15 tmp91fw60 15.10 recommended os cillating conditions the tmp91fw60 has been evaluated by the oscillator vende r below. use this information when selecting external parts. note 1: to ensure stable oscillation, the re sonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: when using the device (oscillator) in places exposed to high elec tric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. note 3: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url: http://www.murata.co.jp/search/index.html x1 x2 c 2 rd c 1 xt1 xt2 c 2 rd c 1 (2) low-frequency oscillation (1) high-frequency oscillation
page 276 2007-10-15 tmp91fw60 16. table of sfr?s the special function registers (sfrs) include the i/o ports and peripheral cont rol registers allocated to the 4-kbyte address space from 000000h to 000fffh. 1. i/o ports 2. i/o port control 3. interrupt control 4. chip select/wait control 5. clock control 6. 8-bit timer 7. 16-bit timer 8. uart/serial channel 9. i 2 c bus interface 10. ad converter 11. watchdog timer 12. special timer for clock 13. program patch logic
page 277 2007-10-15 tmp91fw60 note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). table 16-1 sfr address map (port, intc, cs/wait) [1]port address name address name address name 0000h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh p0 p1 p0cr p1cr p1fc p2 p2cr p2fc p3 p3fc2 p3cr p3fc 0010h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh p4 p4fc2 p4cr p4fc p5 p5cr p5fc p6 p6cr p6fc p7 p7cr p7fc 0020h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh p8 p8cr p8fc p9 p9cr p9fc pa pacr pafc pb pbfc2 pbcr pbfc [2]intc address name address name address name 0030h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh ode 0070h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh pz pzcr pzfc 0080h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh dma0v dma1v dma2v dma3v intclr dmar dmab iimc [3]cs/wait address name address name address name 0090h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh inte0ad inte12 inte34 inte56 inte78 inte910 inteta01 inteta23 inteta45 intetb0 intetb1 intetb2 intetb3 intetb4 intetb01v intetb23v 00a0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh intetb4vrtc intes0 intes1 intes2 intesbi01 intetc01 intetc23 00c0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh b0cs b1cs b2cs b3cs bexcs msar0 mamr0 msar1 mamr1 msar2 mamr2 msar3 mamr3
page 278 2007-10-15 tmp91fw60 note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). table 16-2 sfr address map (cgear, tmra, tmrb) [4] cgear [5] tmra address name address name address name 00e0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh syscr0 syscr1 syscr2 emccr0 emccr1 00f0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh 0100h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh ta01run ta0reg ta1reg ta01mod ta1ffcr ta23run ta2reg ta3reg ta23mod ta3ffcr [6] tmrb address name address name address name 0110h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh ta45run ta4reg ta5reg ta45mod ta5ffcr 0180h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh tb0run tb0mod tb0ffcr tb0rg0l tb0rg0h tb0rg1l tb0rg1h tb0cp0l tb0cp0h tb0cp1l tb0cp1h 0190h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh tb1run tb1mod tb1ffcr tb1rg0l tb1rg0h tb1rg1l tb1rg1h tb1cp0l tb1cp0h tb1cp1l tb1cp1h address name address name address name 01a0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh tb2run tb2mod tb2ffcr tb2rg0l tb2rg0h tb2rg1l tb2rg1h tb2cp0l tb2cp0h tb2cp1l tb2cp1h 01b0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh tb3run tb3mod tb3ffcr tb3rg0l tb3rg0h tb3rg1l tb3rg1h tb3cp0l tb3cp0h tb3cp1l tb3cp1h 01c0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh tb4run tb4mod tb4ffcr tb4rg0l tb4rg0h tb4rg1l tb4rg1h tb4cp0l tb4cp0h tb4cp1l tb4cp1h
page 279 2007-10-15 tmp91fw60 note: do not access to the unnamed addresses (e.g., addresses to which no register has been allocated). table 16-3 sfr address map (uart/sio, i 2 c, adc, wdt, rtc, romc) [7] uart/sio [8] i 2 c address name address name address name 0200h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh sc0buf sc0cr sc0mod0 br0cr br0add sc0mod1 sc1buf sc1cr sc1mod0 br1cr br1add sc1mod1 0210h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh sc2buf sc2cr sc2mod0 br2cr br2add sc2mod1 0240h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh sbi0cr1 sbi0dbr i2c0ar sbi0cr2/sbi0sr sbi0br sbi0cr0 sbi1cr1 sbi1dbr i2c1ar sbi1cr2/sbi1sr sbi1br sbi1cr0 [9]10bit adc [10] wdt [11] rtc address name address name address name 02b0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh adccr1 adccr2 adcdrl adcdrh 0300h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh wdmod wdcr 0310h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh rtccr [12] romc address name address name address name 0400h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh romcmp00 romcmp01 romcmp02 romsub0l romsub0h romcmp10 romcmp11 romcmp12 romsub1l romsub1h 0410h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh romcmp20 romcmp21 romcmp22 romsub2l romsub2h romcmp30 romcmp31 romcmp32 romsub3l romsub3h 0420h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh romcmp40 romcmp41 romcmp42 romsub4l romsub4h romcmp50 romcmp51 romcmp52 romsub5l romsub5h
page 280 2007-10-15 tmp91fw60 (1) i/o ports symbol name address 7 6 5 4 3 2 1 0 p0 port 0 00h p07 p06 p05 p04 p03 p02 p01 p00 r/w data from external port (output latch register is undefined.) p1 port 1 01h p17 p16 p15 p14 p13 p12 p11 p10 r/w data from external port (output latch register is cleared to ?0?.) p2 port 2 06h p27 p26 p25 p24 p23 p22 p21 p20 r/w data from external port (output latch register is set to ?1?.) p3 port 3 0ch ????p33p32p31p30 ???? r/w ???? data from external port (output latch register is set to ?1?.) p4 port 4 10h ? ? ? p44 p43 p42 p41 p40 ??? r/w ??? data from external port (output latch register is set to ?1?.) ??? 0 (output latch register): pull-up resistor off 1 (output latch register): pull-up resistor on p5 port 5 14h p57 p56 p55 p54 p53 p52 p51 p50 r/w data from external port (output latch register is set to ?1?.) p6 port 6 18h p67 p66 p65 p64 p63 p62 p61 p60 r/w data from external port (output latch register is set to ?1?.) p7 port 7 1ch ? ? p75 p74 p73 p72 p71 p70 ?? ? ? ? data from external port (outpu t latch register is set to ?1?.) p8 port 8 20h p87 p86 p85 p84 p83 p82 p81 p80 r/w data from external port (output latch register is set to ?1?.) p9 port 9 24h p97 p96 p95 p94 p93 p92 p91 p90 r/w data from external port (output latch register is set to ?1?.) pa port a 28h ? ? ? ? pa3 pa2 pa1 pa0 ???? r/w ???? data from external port (output latch register is set to ?1?.) pb port b 2ch ? ? ? ? pb3 pb2 pb1 pb0 ???? r/w ???? data from external port (output latch register is set to ?1?.) pz port z 7dh ? ? ? ? pz3 pz2 pz1 pz0 ???? r/w ???? data from external port (output latch register is set to ?1?.) 11 0 (output latch register): pull-up resistor off 1 (output latch register): pull-up resistor on output mode
page 281 2007-10-15 tmp91fw60 (2) i/o port control symbol name address 7 6 5 4 3 2 1 0 p0cr port 0 control 02h (rmw instruc- tions are pro- hibited.) p07c p06c p05c p04c p03c p02c p01c p00c w 00000000 0: input 1: output (when access to external, become ad7 to ad0 and this register is cleared to ?0?.) p1cr port 1 control 04h (rmw instruc- tions are pro- hibited.) p17c p16c p15c p14c p13c p12c p11c p10c w 00000000 <> p1fc port 1 function 05h (rmw instruc- tions are pro- hibited.) p17f p16f p15f p14f p13f p12f p11f p10f w 00000000 p1fc/p1cr = 00: input, 01: output, 10: ad15 to ad8, 11: a15 to a8 p2cr port 2 control 08h (rmw instruc- tions are pro- hibited.) p27c p26c p25c p24c p23c p22c p21c p20c w 00000000 <> p2fc port 2 function 09h (rmw instruc- tions are pro- hibited.) p27f p26f p25f p24f p23f p22f p21f p20f w 00000000 p2fc/p2cr = 00: input, 01: output, 10: a7 to a0, 11: a23 to a16 p3cr port 3 control 0eh (rmw instruc- tions are pro- hibited.) ? ? ? ? p33c p32c p31c p30c ???? w ????0000 ???? <> <> p3fc port 3 function 0fh (rmw instruc- tions are pro- hibited.) ? ? ? ? p33f p32f p31f p30f ???? w ????0000 ???? p33f/ p33c= 00:input port 01:output port 11: tb3out1 p32f/ p32c= 00:input port 01:output port 10: wait 11: tb3out0 <> p3fc2 port 3 function 2 0dh (rmw instruc- tions are pro- hibited.) ??????p31f2p30f2 ?????? w ??????00 ?????? p31f2/ p31f/ p31c= 000:input port 001:output port 010: tb3in1 /int4 101: scl0 p30f2/ p30f/ p30c= 000:input port 001:output port 010: tb3in0 /int3 101: sda0
page 282 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 p4cr port 4 control 12h (rmw instruc- tions are pro- hibited.) ? ? ? p44c p43c p42c p41c p40c ??? w ???00000 ? ? ? <> p4fc port 4 function 13h (rmw instruc- tions are pro- hibited.) ? ? ? p44f p43f p42f p41f p40f ??? w ???00000 ? ? ? <> p4fc2 port 4 function 2 11h (rmw instruc- tions are pro- hibited.) ? ? ? ? p43f2 ? p41f2 p40f2 ????w? w ????0?00 ??? p44f,p44c= 00: input port 01: output prort 11:ale p43f2,p43f ,p43c= 000 :input port 001:output port 011:cs3 101:sclk2 p42f,p42c= 00: input port 01: output port 11:cs2 p41f2,p41f , p41c = 000: input port 001: output port 011:cs1 101:txd2 p40f2,p40f , p40c = 000: input port 001:output port 011: cs0 101: scout p5cr port 5 control 16h (rmw instruc- tions are pro- hibited.) p57c p56c p55c p54c p53c p52c p51c p50c w 00000000 0: input 1: output p5fc port 5 function 17h (rmw instruc- tions are pro- hibited.) p57f p56f p55f p54f p53f p52f p51f p50f w 00000000 p57 input 0: disable 1: enable p56 input 0: disable 1: enable p55 input 0: disable 1: enable p54 input 0: disable 1: enable p53 input 0: disable 1: enable p52 input 0: disable 1: enable p51 input 0: disable 1: enable p50 input 0: disable 1: enable p6cr port 6 control 1ah (rmw instruc- tions are pro- hibited.) p67c p66c p65c p64c p63c p62c p61c p60c w 00000000 0: input 1: output p6fc port 6 function 1bh (rmw instruc- tions are pro- hibited.) p67f p66f p65f p64f p63f p62f p61f p60f w 00000000 p67 input 0: disable 1: enable p66 input 0: disable 1: enable p65 input 0: disable 1: enable p64 input 0: disable 1: enable p63 input 0: disable 1: enable p62 input 0: disable 1: enable p61 input 0: disable 1: enable p60 input 0: disable 1: enable p7cr port 7 control 1eh (rmw instruc- tions are pro- hibited.) ? ? p75c p74c p73c p72c p71c p70c ?? w ??000000 ? ? 0: input 1: output p7fc port 7 function 1fh (rmw instruc- tions are pro- hibited.) ? ? p75f p74f ? p72f p71f ? ??w?w? ??00?00? ?? 0: port 1: int0 0: port 1: ta5out ? 0: port 1: ta3out 0: port 1: ta1out ?
page 283 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 p8cr port 8 control 22h (rmw instruc- tions are pro- hibited.) p87c p86c p85c p84c p83c p82c p81c p80c w 00000000 0: input 1: output p8fc port 8 function 23h (rmw instruc- tions are pro- hibited.) p87f p86f p85f p84f p83f p82f p81f p80f w 00000000 0: port 1: tb1out1 0: port 1: tb1out0 0: port 1: tb1in1, int8 0: port 1: tb1in0, int7 0: port 1: tb0out1 0: port 1: tb0out0 0: port 1: tb0in1, int6 0: port 1: tb0in0, int5 p9cr port 9 control 26h (rmw instruc- tions are pro- hibited.) p97c p96c p95c p94c p93c p92c p91c p90c w 11000000 0: input 1: output p9fc port 9 function 27h (rmw instruc- tions are pro- hibited.) p97f p96f p95f ? p93f p92f ? p90f w?w?w 000?00?0 port 0: disable 1: enable port 0: disable 1: enable 0: port 1: sclk1 output ? 0: port 1: txd1 output 0: port 1: sclk0 output ? 0: port 1: txd0 output pacr port a control 2ah (rmw instruc- tions are pro- hibited.) ? ? ? ? pa3c pa2c pa1c pa0c ???? w ????0000 ? ? ? ? 0: input 1: output pafc port a function 2bh (rmw instruc- tions are pro- hibited.) ? ? ? ? pa3f pa2f pa1f pa0f ???? w ????0000 ???? 0: port 1: tb2out1 0:port 1: tb2out0 0: port 1: tb2in1, int2 0: port 1: tb2in0, int1 pbcr port b control 2eh (rmw instruc- tions are pro- hibited.) ? ? ? ? pb3c pb2c pb1c pb0c ???? w ????0000 ? ? ? ? <> pbfc port b function 2fh (rmw instruc- tions are pro- hibited.) ? ? ? ? pb3f pb2f pb1f pb0f ???? w ????0000 ? ? ? ? <> pbfc2 port b function 2 2dh (rmw instruc- tions are pro- hibited.) ??????pb1f2pb0f2 ?????? w ??????00 ???? pb3f, pb3c = 00: input port 01: output port 11: tb4out1 pb2f, pb2c = 00: input port 01: output port 11: tb4out0 pb1f2,pb1 f, p b 1 c = 000: input port 001: output port 010: tb4in1 /int10 101: scl1 pb0f2,pb0 f, pb0c = 000: input port 001:output port 010: tb4in0 /int9 101: sda1
page 284 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 pzcr port z control 7eh (rmw instruc- tions are pro- hibited.) ? ? ? ? pz3c pz2c ? ? ???? w ?? ????00?? ? ? ? ? 0:input 1:output ? ? pzfc port z function 7fh (rmw instruc- tions are pro- hibited.) ? ? ? ? pz3f pz2f pz1f pz0f ???? w ????0000 ???? 0: port 1:r/ w 0: port 1: hwr 0: port 1: wr 0: port 1: rd ode open-drain control register 3fh ? odeb1 odeb0 ode93 ode90 ode41 ode31 ode30 ?r/w ?0000000 ? 0: cmos output 1:open drain output
page 285 2007-10-15 tmp91fw60 (3) interrupt control symbol name address 7 6 5 4 3 2 1 0 inte0ad interrupt enable 0 & ad 90h intad int0 iadc iadm2 iadm1 iadm0 i0c i0m2 i0m1 i0m0 rr/wrr/w 00000000 1: intad interrput level 1: int0 interrput level inte12 interrupt enable 2 / 1 91h int2 int1 i2c i2m2 i2m1 i2m0 i1c i1m2 i1m1 i1m0 rr/wrr/w 00000000 1: int2 interrput level 1: int1 interrput level inte34 interrupt enable 4 / 3 92h int4 int3 i4c i4m2 i4m1 i4m0 i3c i3m2 i3m1 i3m0 rr/wrr/w 00000000 1: int4 interrput level 1: int3 interrput level inte56 interrupt enable 6 / 5 93h int6 int5 i6c i6m2 i6m1 i6m0 i5c i5m2 i5m1 i5m0 rr/wrr/w 00000000 1: int6 interrput level 1: int5 interrput level inte78 interrupt enable 8 / 7 94h int8 int7 i8c i8m2 i8m1 i8m0 i7c i7m2 i7m1 i7m0 rr/wrr/w 00000000 1: int8 interrput level 1: int7 interrput level inte910 interrupt enable 10 / 9 95h int10 int9 i10c i10m2 i10m1 i10m0 i9c i9m2 i9m1 i9m0 rr/wrr/w 00000000 1: int10 interrput level 1: int9 interrput level inteta01 interrupt enable timer a 1 / 0 96h intta1(tmra1) intta0 (tmra0) ita1c ita1m2 ita1m1 ita1m0 ita0c ita0m2 ita0m1 ita0m0 rr/wrr/w 00000000 1: intta1 interrput level 1: intta0 interrput level inteta23 interrupt enable timer a 3 / 2 97h intta3 (tmra3) intta2 (tmra2) ita3c ita3m2 ita3m1 ita3m0 ita2c ita2m2 ita2m1 ita2m0 rr/wrr/w 00000000 1: intta3 interrput level 1: intta2 interrput level inteta45 interrupt enable timer a 5 / 4 98h intta5 (tmra5) intta4 (tmra4) ita5c ita5m2 ita5m1 ita5m0 ita4c ita4m2 ita4m1 ita4m0 rr/wrr/w 00000000 1: intta5 interrput level 1: intta4 interrput level
page 286 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 intetb0 interrupt enable tmrb 0 99h inttb01(tmrb0) inttb00(tmrb0) itb01c itb01m2 itb01m1 itb01m0 itb00c itb00m2 itb00m1 itb00m0 rr/wrr/w 00000000 1: inttb01 interrput level 1: inttb00 interrput level intetb1 interrupt enable tmrb 1 9ah inttb11(tmrb1) inttb10(tmrb1) itb11c itb11m2 itb11m1 itb11m0 itb10c itb10m2 itb10m1 itb10m0 rr/wrr/w 00000000 1: inttb11 interrput level 1: inttb10 interrput level intetb2 interrupt enable tmrb 2 9bh inttb21(tmrb2) inttb20(tmrb2) itb21c itb21m2 itb21m1 itb21m0 itb20c itb20m2 itb20m1 itb20m0 rr/wrr/w 00000000 1: inttb21 interrput level 1: inttb20 interrput level intetb3 interrupt enable tmrb 3 9ch inttb31(tmrb3) inttb30(tmrb3) itb31c itb31m2 itb31m1 itb31m0 itb30c itb30m2 itb30m1 itb30m0 rr/wrr/w 00000000 1: inttb31 interrput level 1: inttb30 interrput level intetb4 interrupt enable tmrb 4 9dh inttb41(tmrb4) inttb40(tmrb4) itb41c itb41m2 itb41m1 itb41m0 itb40c itb40m2 itb40m1 itb40m0 rr/wrr/w 00000000 1: inttb41 interrput level 1: inttb40 interrput level intetb01v interrupt enable tmrb 0/1 (over flow) 9eh inttbof1(tmrb1 over flow) inttbof1(tmrb0 over flow) itf1c itf1m2 itf1m1 itf1m0 itf0c itf0m2 itf0m1 itf0m0 rr/wrr/w 00000000 1: inttbof1 interrput level 1:inttbof0 interrput level intetb23v interrupt enable tmrb 2/3 (over flow) 9fh inttbof3(tmrb3 over flow) inttbof2(tmrb2 over flow) itf3c itf3m2 itf3m1 itf3m0 itf2c itf2m2 itf2m1 itf2m0 rr/wrr/w 00000000 1: inttbof3 interrput level 1:inttbof2 interrput level intetb4vrtc interrupt enable tmrb4 (over flow) / intrtc a0h intrtc inttbof4(tmrb4 over flow) irtcc irtcm2 irtcm1 irtcm0 itf4c itf4m2 itf4m1 itf4m0 rr/wrr/w 00000000 1: intrtc interrput level 1:inttbof4 interrput level
page 287 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 intes0 interrupt enable serial 0 a1h inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 rr/wrr/w 00000000 1: inttx0 interrput level 1: intrx0 interrput level intes1 interrupt enable serial 1 a2h inttx1 intrx1 itx1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 rr/wrr/w 00000000 1: inttx1 interrput level 1: intrx1 interrput level intes2 interrupt enable serial 2 a3h inttx2 intrx2 itx2c itx2m2 itx2m1 itx2m0 irx0c irx2m2 irx2m1 irx2m0 rr/wrr/w 00000000 1: inttx2 interrput level 1: intrx2 interrput level intesbi01 interrupt enable sbi 0/1 a4h intsbi1 intsbi0 isbi1c isbi1m2 isbi1m1 isbi1m0 isbi0c isbi0m2 isbi0m1 isbi0m0 rr/wrr/w 00000000 1: intsbi1 interrput level 1: intsbi0 interrput level intetc01 interrupt enable tc 0/1 a5h inttc1 inttc0 itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 rr/wrr/w 00000000 1: inttc1 interrput level 1: inttc0 interrput level intetc23 interrupt enable tc 2/3 a6h inttc3 inttc2 itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 rr/wrr/w 00000000 1: inttc3 interrput level 1: inttc2 interrput level
page 288 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 dma0v dma0 start vector 80h ?? dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 ?? r/w ?? 000000 ?? dma0 start vector dma1v dma1 start vector 81h ?? dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 ?? r/w ?? 000000 ?? dma1 start vector dma2v dma2 start vector 82h ?? dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 ?? r/w ?? 000000 ?? dma2 start vector dma3v dma3 start vector 83h ?? dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 ?? r/w ?? 000000 ?? dma3 start vector intclr interrupt clear control 88h (rmw instruc- tions are pro- hibited.) ?? clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 ?? w ?? 000000 ?? interrupt vector dmar dma software request register 89h (rmw instruc- tions are pro- hibited.) ???? dmar3 dmar2 dmar1 dmar0 ???? r/w ???? 0000 ???? 1: dma software request dmab dma burst register 8ah ???? dmab3 dmab2 dmab1 dmab0 ???? r/w ???? 0000 ???? 1: dma burst request iimc interrupt input mode control 8ch (rmw instruc- tions are pro- hibited.) ????? i0edge i0le nmiree w 00000000 always write ?0?. ???? int0 edge 0: rising 1: falling int0 mode 0: edge 1: level 1:oper- ates even on rising/ falling edge of nmi
page 289 2007-10-15 tmp91fw60 (4) chip select / wait control symbol name address 7 6 5 4 3 2 1 0 b0cs block 0 cs/wait control register c0h (rmw instruc- tions are pro- hibited.) b0e ? b0om1 b0om0 b0bus b0w2 b0w1 b0w0 w ? w 0 ? 000000 0: disable 1: enable ? chip select output wave- form selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait b1cs block 1 cs/wait control register c1h (rmw instruc- tions are pro- hibited.) b1e ? b1om1 b1om0 b1bus b1w2 b1w1 b1w0 w ? w 0 ? 000000 0: disable 1: enable ? chip select output wave- form selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait b2cs block 2 cs/wait control register c2h (rmw instruc- tions are pro- hibited.) b2e b2m b2om1 b2om0 b2bus b2w2 b2w1 b2w0 w 10000000 0: disable 1: enable cs2 area selection 0:16mbyte area 1: cs area chip select output wave- form selection 00: rom/sram 01: don't care 10: don't care 11: don't care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait b3cs block 3 cs/wait control register c3h (rmw instruc- tions are pro- hibited.) b3e ? b3om1 b3om0 b3bus b3w2 b3w1 b3w0 w ? w 0 ? 000000 0: disable 1: enable ? chip select output wave- form selection 00: for rom/sram 01: don?t care 10: don?t care 11: don?t care data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait bexcs external cs/wait control register c7h (rmw instruc- tions are pro- hibited.) ???? bexbus bexw2 bexw1 bexw0 ? ? ?? w ?? ?? 0000 ???? data bus width 0: 16 bits 1: 8 bits number of waits 000: 2 wait 100: reserved 001: 1 wait 101: 3 wait 010: 1 wait+n 110: 4 wait 011: 0 wait 111: 8 wait
page 290 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 msar0 memory address register 0 c8h s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 determine a23 to a16 of start address mamr0 memory address mask register 0 c9h v20 v19 v18 v17 v16 v15 v14~v9 v8 r/w 11111111 set size of cs0 area 0: used for address compare msar1 memory address register 1 cah s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 determine a23 to a16 of start address mamr1 memory address mask register 1 cbh v21 v20 v19 v18 v17 v16 v15~v9 v8 r/w 11111111 set size of cs1 area 0: used for address compare msar2 memory address register 2 cch s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 determine a23 to a16 of start address mamr2 memory address mask register 2 cdh v22 v21 v20 v19 v18 v17 v16 v15 r/w 11111111 set size of cs2 area 0: used for address compare msar3 memory address register 3 ceh s23 s22 s21 s20 s19 s18 s17 s16 r/w 11111111 determine a23 to a16 of start address mamr3 memory address mask register 3 cfh v22 v21 v20 v19 v18 v17 v16 v15 r/w 11111111 set size of cs3 area 0: used for address compare
page 291 2007-10-15 tmp91fw60 (5) clock control symbol name address 7 6 5 4 3 2 1 0 syscr0 system clock control register 0 e0h xen xten rxen rxten rsysck wuef prck1 ? r/w ? 1010000? high- frequency oscillator 0:stop 1:oscilla- tion low- frequency oscillator 0:stop 1:oscilla- tion high- frequency oscillator (fc) after release of stop mode 0:stop 1:oscilla- tion low- frequency oscillator (fs) after release of stop mode 0:stop 1:oscilla- tion selects clock after release of stop mode 0:fc 1:fs warm-up timer con- trol 0 write: don't care 1 write: start warm-up 0 read: end warm- up 1 read: do not end warm-up select prescaler clock 0:f fph 1:fc/16 ? syscr1 system clock control register 1 e1h ? ? ? ? sysck gear2 gear2 gear2 ???? r/w ????0000 ???? select sys- tem clock 0: fc 1: fs select gear value of high frequency (fc) 000:fc 001:fc/2 010:fc/4 011:fc/8 100:fc/16 101:reserved 110:reserved 111:reserved syscr2 system clock control register 1 e2h ? scosel wuptm1 wuptm0 haltm1 haltm0 ? drve ?r/w?r/w ?01011?0 ? select scout 0:fs 1:f sys select warm-up time for oscillator 00:2 18 /inputted fre- quency 01:2 8 /inputted frequency 10:2 14 /inputted fre- quency 11:2 16 /inputted fre- quency halt mode 00:reserved 01:stop mode 10:idle1 mode 11:idle2 mode ? pin state control in stop mode 0: i/o off 1:remains the state before halt emccr0 emc control register 0 e3h protect??????? rr/w 00100011 protect flag 0:off 1:on write "0". write "1". write "0". write "0". write "0". write "1". write "1". emccr1 emc control register 1 e4h protect off by writing "1fh". protect on by writing except "1fh".
page 292 2007-10-15 tmp91fw60 (6) 8-bit timer symbol name address 7 6 5 4 3 2 1 0 ta01run 8-bit timer run 100h ta0rde ? ? ? i2ta01 ta01prun ta1run ta0run r/w ? ? ? r/w 0???0000 double buffer 0: disable 1: enable ??? idle2 0: stop 1: operate tmra01 prescaler up counter (uc1) up counter (uc0) 0: stop and clear 1: run (count up) ta0reg 8-bit timer register 0 102h (rmw instruc- tions are pro- hibited.) ? w 0 ta1reg 8-bit timer register 1 103h (rmw instruc- tions are pro- hibited.) ? w 0 ta01mod 8-bit timer source clk & mode 104h ta01m1 ta01m0 pwm01 pwm00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 r/w 00000000 operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 input clock for tmra1 00: ta0trg 01: t1 10: t16 11: t256 input clock for tmra0 00: ta0in pin 01: t1 10: t4 11: t16 ta1ffcr 8-bit timer frip-flop control 105h ? ? ? ? ta1ffc1 ta1ffc0 ta1ffie ta1ffis ???? r/w ????1100 ???? 00: invert ta1ff 01: set ta1ff 10: clear ta1ff 11: don?t care ta1ff control for inversion 0: disable 1: enable ta1ff inversion select 0: tmra0 1: tmra1
page 293 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 ta23run 8-bit timer run 108h ta2rde ? ? ? i2ta23 ta23prun ta3run ta2run r/w ? ? ? r/w 0???0000 double buffer 0: disable 1: enable ??? idle2 0: stop 1: operate tmra23 prescaler up counter (uc3) up counter (uc2) 0: stop and clear 1: run (count up) ta2reg 8-bit timer register 0 10ah (rmw instruc- tions are pro- hibited.) ? w 0 ta3reg 8-bit timer register 1 10bh (rmw instruc- tions are pro- hibited.) ? w 0 ta23mod 8-bit timer source clk & mode 10ch ta23m1 ta23m0 pwm21 pwm20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 r/w 00000000 operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 input clock for tmra3 00: ta2trg 01: t1 10: t16 11: t256 input clock for tmra2 00: reserved 01: t1 10: t4 11: t16 ta3ffcr 8-bit timer frip-flop control 10dh ? ? ? ? ta3ffc1 ta3ffc0 ta3ffie ta3ffis ???? r/w ????1100 ???? 00: invert ta3ff 01: set ta3ff 10: clear ta3ff 11: don?t care ta3ff control for inversion 0: disable 1: enable ta3ff inversion select 0: tmra2 1: tmra3
page 294 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 ta45run 8-bit timer run 110h ta4rde ? ? ? i2ta45 ta45prun ta5run ta4run r/w ? ? ? r/w 0???0000 double buffer 0: disable 1: enable ??? idle2 0: stop 1: operate tmra45 prescaler up counter (uc5) up counter (uc4) 0: stop and clear 1: run (count up) ta4reg 8-bit timer register 0 112h (rmw instruc- tions are pro- hibited.) ? w 0 ta5reg 8-bit timer register 1 113h (rmw instruc- tions are pro- hibited.) ? w 0 ta45mod 8-bit timer source clk & mode 114h ta45m1 ta45m0 pwm41 pwm40 ta5clk1 ta5clk0 ta4clk1 ta4clk0 r/w 00000000 operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 input clock for tmra5 00: ta4trg 01: t1 10: t16 11: t256 input clock for tmra4 00: ta4in pin 01: t1 10: t4 11: t16 ta5ffcr 8-bit timer frip-flop control 115h ? ? ? ? ta5ffc1 ta5ffc0 ta5ffie ta5ffis ???? r/w ????1100 ???? 00: invert ta5ff 01: set ta5ff 10: clear ta5ff 11: don?t care ta5ff control for inversion 0: disable 1: enable ta5ff inversion select 0: tmra4 1: tmra5
page 295 2007-10-15 tmp91fw60 (7) 16-bit timer symbol name address 7 6 5 4 3 2 1 0 tb0run 16-bit timer control 180h tb0rde ? ? ? i2tb0 tb0prun ? tb0run r/w ? ? r/w ? r/w 00??00?0 double buffer 0: disable 1: enable always write 0. ?? idle2 0: stop 1: operate tmrb0 prescaler ? up counter (uc0) 0: stop and clear 1: run (count up) tb0mod 16-bit timer source clk & mode 182h (rmw instruc- tions are pro- hibited.) tb0ct1 tb0et1 tb0cp0i tb0cpm1 tb0cpm0 tb0cle tb0clk1 tb0clk0 r/w w* r/w 00100000 tb0ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: unde- fined capture timing 00: disable int5 occurs at rising edge 01: tb0in0 tb0in1 int5 occurs at rising edge 10: tb0in0 tb0in0 int5 occurs at falling edge 11: ta1out ta1out int5 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb0 input clock select 00: tb0in0 pin input 01: t1 10: t4 11: t16 invert when uc0 is loaded into tb0cp1h/l invert when uc0 matches with tb0rg1h/l tb0ffcr 16-bit timer frip-flop control 183h (rmw instruc- tions are pro- hibited.) tb0ff1c1 tb0ff1c0 tb0c1t1 tb0c0t1 tb0e1t1 tb0e0t1 tb0ff0c1 tb0ff0c0 w* r/w w* 11000011 tb0ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb0ff0 inversion trigger 0: disable 1: enable tb0ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc0 is loaded into tb0cp1h/l. invert when uc0 is loaded into tb0cp0h/l. invert when uc0 matches tb0rg1h/l. invert when uc0 matches tb0rg0h/l. tb0rg0l 16-bit timer register 0l 188h (rmw instruc- tions are pro- hibited.) ? w undefined tb0rg0h 16-bit timer register 0h 189h (rmw instruc- tions are pro- hibited.) ? w undefined tb0rg1l 16-bit timer register 1l 18ah (rmw instruc- tions are pro- hibited.) ? w undefined tb0rg1h 16-bit timer register 1h 18bh (rmw instruc- tions are pro- hibited.) ? w undefined tb0cp0l capture register 0l 18ch ? r undefined tb0cp0h capture register 0h 18dh ? r undefined tb0cp1l capture register 1l 18eh ? r undefined tb0cp1h capture register 1h 18fh ? r undefined
page 296 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 tb1run 16-bit timer control 190h tb1rde ? ? ? i2tb1 tb1prun ? tb1run r/w ? ? r/w ? r/w 00??00?0 double buffer 0: disable 1: enable always write 0. ?? idle2 0: stop 1: operate tmrb1 prescaler ? up counter (uc1) 0: stop and clear 1: run (count up) tb1mod 16-bit timer source clk & mode 192h (rmw instruc- tions are pro- hibited.) tb1ct1 tb1et1 tb1cp0i tb1cpm1 tb1cpm0 tb1cle tb1clk1 tb1clk0 r/w w* r/w 00100000 tb1ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: unde- fined capture timing 00: disable int7 occurs at rising edge 01: tb1in0 tb1in1 int7 occurs at rising edge 10: tb1in0 tb1in0 int7 occurs at falling edge 11: ta1out ta1out int7 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb1 input clock select 00: tb1in0 pin input 01: t1 10: t4 11: t16 invert when uc1 is loaded into tb1cp1h/l invert when uc1 matches with tb1rg1h/l tb1ffcr 16-bit timer frip-flop control 193h (rmw instruc- tions are pro- hibited.) tb1ff1c1 tb1ff1c0 tb1c1t1 tb1c0t1 tb1e1t1 tb1e0t1 tb1ff0c1 tb1ff0c0 w* r/w w* 11000011 tb1ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb1ff0 inversion trigger 0: disable 1: enable tb1ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc1 is loaded into tb1cp1h/l. invert when uc1 is loaded into tb1cp0h/l. invert when uc1 matches tb1rg1h/l. invert when uc1 matches tb1rg0h/l. tb1rg0l 16-bit timer register 0l 198h (rmw instruc- tions are pro- hibited.) ? w undefined tb1rg0h 16-bit timer register 0h 199h (rmw instruc- tions are pro- hibited.) ? w undefined tb1rg1l 16-bit timer register 1l 19ah (rmw instruc- tions are pro- hibited.) ? w undefined tb1rg1h 16-bit timer register 1h 19bh (rmw instruc- tions are pro- hibited.) ? w undefined tb1cp0l capture register 0l 19ch ? r undefined tb1cp0h capture register 0h 19dh ? r undefined tb1cp1l capture register 1l 19eh ? r undefined tb1cp1h capture register 1h 19fh ? r undefined
page 297 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 tb2run 16-bit timer control 1a0h tb2rde ? ? ? i2tb2 tb2prun ? tb2run r/w ? ? r/w ? r/w 00??00?0 double buffer 0: disable 1: enable always write 0. ?? idle2 0: stop 1: operate tmrb2 prescaler ? up counter (uc2) 0: stop and clear 1: run (count up) tb2mod 16-bit timer source clk & mode 1a2h (rmw instruc- tions are pro- hibited.) tb2ct1 tb2et1 tb2cp0i tb2cpm1 tb2cpm0 tb2cle tb2clk1 tb2clk0 r/w w* r/w 00100000 tb2ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: unde- fined capture timing 00: disable int1 occurs at rising edge 01: tb2in0 tb2in1 int1 occurs at rising edge 10: tb2in0 tb2in0 int1 occurs at falling edge 11: ta1out ta1out int1 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb2 input clock select 00: tb2in0 pin input 01: t1 10: t4 11: t16 invert when uc2 is loaded into tb2cp1h/l invert when uc2 matches with tb2rg1h/l tb2ffcr 16-bit timer frip-flop control 1a3h (rmw instruc- tions are pro- hibited.) tb2ff1c1 tb2ff1c0 tb2c1t1 tb2c0t1 tb2e1t1 tb2e0t1 tb2ff0c1 tb2ff0c0 w* r/w w* 11000011 tb2ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb2ff0 inversion trigger 0: disable 1: enable tb2ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc2 is loaded into tb2cp1h/l. invert when uc2 is loaded into tb2cp0h/l. invert when uc2 matches tb2rg1h/l. invert when uc2 matches tb2rg0h/l. tb2rg0l 16-bit timer register 0l 1a8h (rmw instruc- tions are pro- hibited.) ? w undefined tb2rg0h 16-bit timer register 0h 1a9h (rmw instruc- tions are pro- hibited.) ? w undefined tb2rg1l 16-bit timer register 1l 1aah (rmw instruc- tions are pro- hibited.) ? w undefined tb2rg1h 16-bit timer register 1h 1abh (rmw instruc- tions are pro- hibited.) ? w undefined tb2cp0l capture register 0l 1ach ? r undefined tb2cp0h capture register 0h 1adh ? r undefined tb2cp1l capture register 1l 1aeh ? r undefined tb2cp1h capture register 1h 1afh ? r undefined
page 298 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 tb3run 16-bit timer control 1b0h tb3rde ? ? ? i2tb3 tb3prun ? tb3run r/w ? ? r/w ? r/w 00??00?0 double buffer 0: disable 1: enable always write 0. ?? idle2 0: stop 1: operate tmrb3 prescaler ? up counter (uc3) 0: stop and clear 1: run (count up) tb3mod 16-bit timer source clk & mode 1b2h (rmw instruc- tions are pro- hibited.) tb3ct1 tb3et1 tb3cp0i tb3cpm1 tb3cpm0 tb3cle tb3clk1 tb3clk0 r/w w* r/w 00100000 tb3ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: unde- fined capture timing 00: disable int3 occurs at rising edge 01: tb3in0 tb3in1 int3 occurs at rising edge 10: tb3in0 tb3in0 int3 occurs at falling edge 11: ta3out ta3out int3 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb3 input clock select 00: tb3in0 pin input 01: t1 10: t4 11: t16 invert when uc3 is loaded into tb3cp1h/l invert when uc3 matches with tb3rg1h/l tb3ffcr 16-bit timer frip-flop control 1b3h (rmw instruc- tions are pro- hibited.) tb3ff1c1 tb3ff1c0 tb3c1t1 tb3c0t1 tb3e1t1 tb3e0t1 tb3ff0c1 tb3ff0c0 w* r/w w* 11000011 tb3ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb3ff0 inversion trigger 0: disable 1: enable tb3ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc3 is loaded into tb3cp1h/l. invert when uc3 is loaded into tb3cp0h/l. invert when uc3 matches tb3rg1h/l. invert when uc3 matches tb3rg0h/l. tb3rg0l 16-bit timer register 0l 1b8h (rmw instruc- tions are pro- hibited.) ? w undefined tb3rg0h 16-bit timer register 0h 1b9h (rmw instruc- tions are pro- hibited.) ? w undefined tb3rg1l 16-bit timer register 1l 1bah (rmw instruc- tions are pro- hibited.) ? w undefined tb3rg1h 16-bit timer register 1h 1bbh (rmw instruc- tions are pro- hibited.) ? w undefined tb3cp0l capture register 0l 1bch ? r undefined tb3cp0h capture register 0h 1bdh ? r undefined tb3cp1l capture register 1l 1beh ? r undefined tb3cp1h capture register 1h 1bfh ? r undefined
page 299 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 tb4run 16-bit timer control 1c0h tb4rde ? ? ? i2tb4 tb4prun ? tb4run r/w ? ? r/w ? r/w 00??00?0 double buffer 0: disable 1: enable always write 0. ?? idle2 0: stop 1: operate tmrb4 prescaler ? up counter (uc4) 0: stop and clear 1: run (count up) tb4mod 16-bit timer source clk & mode 1c2h (rmw instruc- tions are pro- hibited.) tb4ct1 tb4et1 tb4cp0i tb4cpm1 tb4cpm0 tb4cle tb4clk1 tb4clk0 r/w w* r/w 00100000 tb4ff1 inversion trigger 0: trigger disable 1: trigger enable software capture control 0: software capture 1: unde- fined capture timing 00: disable int9 occurs at rising edge 01: tb4in0 tb4in1 int9 occurs at rising edge 10: tb4in0 tb4in0 int9 occurs at falling edge 11: ta5out ta5out int9 occurs at rising edge up counter control 0: clear disable 1: clear enable tmrb4 input clock select 00: tb4in0 pin input 01: t1 10: t4 11: t16 invert when uc4 is loaded into tb4cp1h/l invert when uc4 matches with tb4rg1h/l tb4ffcr 16-bit timer frip-flop control 1c3h (rmw instruc- tions are pro- hibited.) tb4ff1c1 tb4ff1c0 tb4c1t1 tb4c0t1 tb4e1t1 tb4e0t1 tb4ff0c1 tb4ff0c0 w* r/w w* 11000011 tb4ff1 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. tb4ff0 inversion trigger 0: disable 1: enable tb4ff0 control 00: invert 01: set 10: clear 11: don?t care note: always read as 11. invert when uc4 is loaded into tb4cp1h/l. invert when uc4 is loaded into tb4cp0h/l. invert when uc4 matches tb4rg1h/l. invert when uc4 matches tb4rg0h/l. tb4rg0l 16-bit timer register 0l 1c8h (rmw instruc- tions are pro- hibited.) ? w undefined tb4rg0h 16-bit timer register 0h 1c9h (rmw instruc- tions are pro- hibited.) ? w undefined tb4rg1l 16-bit timer register 1l 1cah (rmw instruc- tions are pro- hibited.) ? w undefined tb4rg1h 16-bit timer register 1h 1cbh (rmw instruc- tions are pro- hibited.) ? w undefined tb4cp0l capture register 0l 1cch ? r undefined tb4cp0h capture register 0h 1cdh ? r undefined tb4cp1l capture register 1l 1ceh ? r undefined tb4cp1h capture register 1h 1cfh ? r undefined
page 300 2007-10-15 tmp91fw60 (8) uart / serial channel symbol name address 7 6 5 4 3 2 1 0 sc0buf serial channel 0 buffer 200h (rmw instruc- tions are pro- hibited.) rb7 / tb7 rb6 / tb6 rb5 / tb5 rb4 / tb4 rb3 / tb3 rb2 / tb2 rb1 / tb1 rb0 / tb0 r (receiving) / w (transmission) undefined sc0cr serial channel 0 control 201h (rmw instruc- tions are pro- hibited.) rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to "0" when read) r/w undefined 0 0 0 0 0 0 0 received data bit8 parity 0: odd 1: even parity addition 0: disable 1: enable overrun error flag 0: unde- tect error 1: detect error parity error flag 0: unde- tect error 1: detect error framing error flag 0: unde- tect error 1: detect error edge selection for sclk pin (i/o mode) 0: sclk 1: sclk i/o inter- face input clock selection 0: baud rate gener- ator 1: sclk pin input sc0mod0 serial channel 0 mode 0 202h tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmis- sion data bit8 hand- shake function 0: disable 1: enable receive function 0: disable 1: enable wakeup function 0: disable 1: enable serial transmission mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial transmission clock (uart) 00: timer ta0trg 01: baud rate generator 10: internal clock f sys 11: external clock (sclk input) br0cr baud ratel control 203h ? br0adde br0ck1 br0ck0 br0s3 br0s2 br0s1 br0s0 r/w 00000000 always write 0. + (16 - k)/ 16 division 0: disable 1: enable input clock selection for baud rate generator 00: t0 01: t2 10: t8 11: t32 setting of the divided frequency ?n? br0add serial channel 0 k setting register 204h ? ? ? ? br0k3 br0k2 br0k1 br0k0 ???? r/w ????0000 ???? sets frequency divisor ?k? (divided by n + (16 - k)/16) sc0mod1 serial channel 0 mode 1 205h i2s0 fdpx0 ? ? ? ? ? ? r/w ?????? 00?????? idle2 0: stop 1: run duplex 0: half 1: full ??????
page 301 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 sc1buf serial channel 1 buffer 208h (rmw instruc- tions are pro- hibited.) rb7 / tb7 rb6 / tb6 rb5 / tb5 rb4 / tb4 rb3 / tb3 rb2 / tb2 rb1 / tb1 rb0 / tb0 r (receiving) / w (transmission) undefined sc1cr serial channel 1 control 209h (rmw instruc- tions are pro- hibited.) rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to "0" when read) r/w undefined 0 0 0 0 0 0 0 received data bit8 parity 0: odd 1: even parity addition 0: disable 1: enable overrun error flag 0: unde- tect error 1: detect error parity error flag 0: unde- tect error 1: detect error framing error flag 0: unde- tect error 1: detect error edge selection for sclk pin (i/o mode) 0: sclk 1: sclk i/o inter- face input clock selection 0: baud rate gener- ator 1: sclk pin input sc1mod0 serial channel 1 mode 0 20ah tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmis- sion data bit8 hand- shake function 0: disable 1: enable receive function 0: disable 1: enable wakeup function 0: disable 1: enable serial transmission mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial transmission clock (uart) 00: timer ta0trg 01: baud rate generator 10: internal clock f sys 11: external clock (sclk input) br1cr baud ratel control 20bh ? br1adde br1ck1 br1ck0 br1s3 br1s2 br1s1 br1s0 r/w 00000000 always write ?0?. + (16 - k)/ 16 division 0: disable 1: enable input clock selection for baud rate generator 00: t0 01: t2 10: t8 11: t32 setting of the divided frequency ?n? br1add serial channel 1 k setting register 20ch ? ? ? ? br1k3 br1k2 br1k1 br1k0 ???? r/w ????0000 ???? sets frequency divisor ?k? (divided by n + (16 - k)/16) sc1mod1 serial channel 1 mode 1 20dh i2s1 fdpx1 ? ? ? ? ? ? r/w ?????? 00?????? idle2 0: stop 1: run duplex 0: half 1: full ??????
page 302 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 sc2buf serial channel 2 buffer 210h (rmw instruc- tions are pro- hibited.) rb7 / tb7 rb6 / tb6 rb5 / tb5 rb4 / tb4 rb3 / tb3 rb2 / tb2 rb1 / tb1 rb0 / tb0 r (receiving) / w (transmission) undefined sc2cr serial channel 2 control 211h (rmw instruc- tions are pro- hibited.) rb8 even pe oerr perr ferr sclks ioc r r/w r (cleared to "0" when read) r/w undefined 0 0 0 0 0 0 0 received data bit8 parity 0: odd 1: even parity addition 0: disable 1: enable overrun error flag 0: unde- tect error 1: detect error parity error flag 0: unde- tect error 1: detect error framing error flag 0: unde- tect error 1: detect error edge selection for sclk pin (i/o mode) 0: sclk 1: sclk i/o inter- face input clock selection 0: baud rate gener- ator 1: sclk pin input sc2mod0 serial channel 2 mode 0 212h tb8 ctse rxe wu sm1 sm0 sc1 sc0 r/w 00000000 transmis- sion data bit8 hand- shake function 0: disable 1: enable receive function 0: disable 1: enable wakeup function 0: disable 1: enable serial transmission mode 00: i/o interface mode 01: 7-bit uart mode 10: 8-bit uart mode 11: 9-bit uart mode serial transmission clock (uart) 00: timer ta0trg 01: baud rate generator 10: internal clock f sys 11: external clock (sclk input) br2cr baud ratel control 213h ? br2adde br2ck1 br2ck0 br2s3 br2s2 br2s1 br2s0 r/w 00000000 always write ?0?. + (16 - k)/ 16 division 0: disable 1: enable input clock selection for baud rate generator 00: t0 01: t2 10: t8 11: t32 setting of the divided frequency ?n? br2add serial channel 2 k setting register 214h ? ? ? ? br2k3 br2k2 br2k1 br2k0 ???? r/w ????0000 ???? sets frequency divisor ?k? (divided by n + (16 - k)/16) sc2mod1 serial channel 2 mode 1 215h i2s2 fdpx2 ? ? ? ? ? ? r/w ?????? 00?????? idle2 0: stop 1: run duplex 0: half 1: full ??????
page 303 2007-10-15 tmp91fw60 (9) i 2 c bus interface symbol name address 7 6 5 4 3 2 1 0 sbi0cr1 serial bus interface control register 1 240h (rmw instruc- tions are pro- hibited.) bc2 bc1 bc0 ack ? sck2 sck1 swrmon /sck0 wr/w?wr/w 0000?000/1 number of transferred bits 000: 8 001: 1 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7 acknowl- edge clock 0: disable 1: enable ? at write internal serial clock selection and soft- ware reset monitor 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111:reserved at read 0: during software reset sbi0dbr sbi buffer register 241h (rmw instruc- tions are pro- hibited.) db7 db6 db5 db4 db3 db2 db1 db0 r (receiving) / w (transmission) undefined i2c0ar i 2 c bus address register 242h (rmw instruc- tions are pro- hibited.) sa6 sa5 sa4 sa3 sa2 sa1 sa0 als w 00000000 slave address selection for when device is operating as slave device address recognition 0: enable 1: disable when read sbi0sr serial bus interface status register 243h (rmw instruc- tions are pro- hibited.) mst trx bb pin al/ sbim1 aas/ sbim0 ad0/ swrst1 lrb/ swrst0 r/w 00010000 0: slave 1: master 0:receiver 1:transmit bus status monitor 0: free 1: busy[ intsbi request monitor 0: request 1: cancel arbitration lost detection monitor 1: detect slave address match detection monitor 1:detect general call detection 1: detect last receive bit monitor 0: ?0? 1: ?1? when write sbi0cr2 serial bus interface control register 2 start/stop condition 0: start condition 1: stop condition cancel intsbi interrupt request 0: ? 1: cancel serial bus interface operating mode selec- tion 00: port mode 01: reserved 10: i 2 c bus mode 11: reserved software reset generate write ?10? and ?01?, then an internal reset signal is generated. sbi0br serial bus interface baud rate register 244h (rmw instruc- tions are pro- hibited.) ?i2sbi0? ? ? ? ? ? wr/w?????r/w 00?????0 always write ?0? operation in idle2 mode 0: stop 1: operate ????? always write ?0? sbi0cr0 serial bus interface control register 0 247h (rmw instruc- tions are pro- hibited.) sbi0en??????? r/w r 00000000 sbi operation 0: disable 1: enable always read "0".
page 304 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 sbi1cr1 serial bus interface control register 1 248h (rmw instruc- tions are pro- hibited.) bc2 bc1 bc0 ack ? sck2 sck1 sck0/ swrmon wr/w?wr/w 0000?000/1 number of transferred bits 000: 8 001: 1 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7 acknowl- edge clock 0: disable 1: enable ? at write internal serial clock selection and soft- ware reset monitor 000: 4 001: 5 010: 6 011: 7 100: 8 101: 9 110: 10 111:reserved at read 0: during software reset sbi1dbr sbi buffer register 249h (rmw instruc- tions are pro- hibited.) db7 db6 db5 db4 db3 db2 db1 db0 r (receiving) / w (transmission) ?s? i2c1ar i 2 c bus address register 24ah (rmw instruc- tions are pro- hibited.) sa6 sa5 sa4 sa3 sa2 sa1 sa0 als w 00000000 slave address selection for when device is operating as slave device address recognition 0: enable 1: disable when read sbi1sr serial bus interface status register 24bh (rmw instruc- tions are pro- hibited.) mst trx bb pin al/ sbim1 aas/ sbim0 ad0/ swrst1 lrb/ swrst0 r/w 00010000 0: slave 1: master 0:receiver 1:transmit bus status monitor 0: free 1: busy[ intsbi request monitor 0: request 1: cancel arbitration lost detection monitor 1: detect slave address match detection monitor 1:detect general call detection 1: detect last receive bit monitor 0: ?0? 1: ?1? when write sbi1cr2 serial bus interface control register 2 start/stop condition 0: start condition 1: stop condition cancel intsbi interrupt request 0: ? 1: cancel serial bus interface operating mode selec- tion 00: port mode 01: reserved 10: i 2 c bus mode 11: reserved software reset generate write ?10? and ?01?, then an internal reset signal is generated. sbi1br serial bus interface baud rate register 24ch (rmw instruc- tions are pro- hibited.) ?i2sbi1? ? ? ? ? ? wr/w?????r/w 00?????0 always write ?0? operation in idle2 mode 0: stop 1: operate ????? always write ?0? sbi1cr0 serial bus interface control register 0 24fh (rmw instruc- tions are pro- hibited.) sbi1en??????? r/w r 00000000 sbi operation 0: disable 1: enable always read "0".
page 305 2007-10-15 tmp91fw60 (10) ad converter symbol name address 7 6 5 4 3 2 1 0 adccr1 ad control register 1 2b0h adrs amd ainen sain r/w 00000000 ad con- version start 0: - 1: ad con- version start ad operating mode 00: ad operation disable 01: single mode 10: reserved 11: repeat mode analog input con- trol 0: disable 1: enable analog input channel select 0000: an0 0100: an4 1000: an8 1100: an12 0001: an1 0101: an5 1001: an9 1101: an13 0010: an2 0110: an6 1010: an10 1110: an14 0011: an3 0111: an7 1011: an11 1111: an15 adccr2 ad control register 2 2b1h eocf adbf rsel i2ad ack rr/w 00001100 ad con- version end flag 0:before or during conversion 1: conver- sion com- pleted ad con- version busy flag 0: during stop of ad conversion 1: during ad con- version storing of an ad conver- sion result 0: 10bit mode 1: 8bit mode idle2 control 0:stop 1:opera- tion ad conversion time select 1010: 78 / fc [s] 1011: 156 / fc [s] 1100: 312 / fc [s] 1101: 624 / fc [s] 1110: 1248 / fc [s] adcdrl ad result register l 2b2h ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 r 00000000 adcdrh when 10-bit storing mode ad result register h 2b3h ??????ad09ad08 r 00000000 adcdrh when 8-bit storing mode ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 r 00000000
page 306 2007-10-15 tmp91fw60 (11) watchdog timer symbol name address 7 6 5 4 3 2 1 0 wdmod wdt mode register 300h wdte wdtp1 wdtp0 ? ? i2wdt rescr ? r/w ? ? r/w 000??000 wdt control 1: enable select detecting time 00: 2 15 /f sys 01: 2 17 /f sys 10: 2 19 /f sys 11: 2 21 /f sys ?? idle2 0: stop 1: operate 1: inter- mally con- nects wdt out to the reset pin always write ?0?. wdcr wdt control 301h (rmw instruc- tions are pro- hibited.) ? w ? b1h: wdt disable code 4eh: wdt clear code (12) special timer for clock symbol name address 7 6 5 4 3 2 1 0 rtccr rtc control register 310h ? ? ? ? ? rtcsel1 rtcsel0 rtcrun r/w???? r/w 0????000 always write ?0?. ???? 00: 2 14 /fs 01: 2 13 /fs 10: 2 12 /fs 11: 2 11 /fs 0: stop & clear 1: count
page 307 2007-10-15 tmp91fw60 (13) program patch logic symbol name address 7 6 5 4 3 2 1 0 romcmp00 address compare register 00 400h (rmw instruc- tions are pro- hibited.) romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? w? 0000000? target rom address (lower 7 bits) ? romcmp01 address compare register 01 401h (rmw instruc- tions are pro- hibited.) romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 w 00000000 target rom address (middle 8 bits) romcmp02 address compare register 02 402h (rmw instruc- tions are pro- hibited.) romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 w 00000000 target rom address (upper 8 bits) romsub0l address substitution register 0l 404h (rmw instruc- tions are pro- hibited.) roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 w 00000000 patch code (lower 8 bits) romsub0h address substitution register 0h 405h (rmw instruc- tions are pro- hibited.) roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 w 00000000 patch code (upper 8 bits) romcmp10 address compare register 10 408h (rmw instruc- tions are pro- hibited.) romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? w? 0000000? target rom address (lower 7 bits) ? romcmp11 address compare register 11 409h (rmw instruc- tions are pro- hibited.) romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 w 00000000 target rom address (middle 8 bits) romcmp12 address compare register 12 40ah (rmw instruc- tions are pro- hibited.) romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 w 00000000 target rom address (upper 8 bits) romsub1l address substitution register 1l 40ch (rmw instruc- tions are pro- hibited.) roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 w 00000000 patch code (lower 8 bits) romsub1h address substitution register 1h 40dh (rmw instruc- tions are pro- hibited.) roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 w 00000000 patch code (upper 8 bits)
page 308 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 romcmp20 address compare register 20 410h (rmw instruc- tions are pro- hibited.) romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? w? 0000000? target rom address (lower 7 bits) ? romcmp21 address compare register 21 411h (rmw instruc- tions are pro- hibited.) romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 w 00000000 target rom address (middle 8 bits) romcmp22 address compare register 22 412h (rmw instruc- tions are pro- hibited.) romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 w 00000000 target rom address (upper 8 bits) romsub2l address substitution register 2l 414h (rmw instruc- tions are pro- hibited.) roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 w 00000000 patch code (lower 8 bits) romsub2h address substitution register 2h 415h (rmw instruc- tions are pro- hibited.) roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 w 00000000 patch code (upper 8 bits) romcmp30 address compare register 30 418h (rmw instruc- tions are pro- hibited.) romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? w? 0000000? target rom address (lower 7 bits) ? romcmp31 address compare register 31 419h (rmw instruc- tions are pro- hibited.) romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 w 00000000 target rom address (middle 8 bits) romcmp32 address compare register 32 41ah (rmw instruc- tions are pro- hibited.) romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 w 00000000 target rom address (upper 8 bits) romsub3l address substitution register 3l 41ch (rmw instruc- tions are pro- hibited.) roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 w 00000000 patch code (lower 8 bits) romsub3h address substitution register 3h 41dh (rmw instruc- tions are pro- hibited.) roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 w 00000000 patch code (upper 8 bits)
page 309 2007-10-15 tmp91fw60 symbol name address 7 6 5 4 3 2 1 0 romcmp40 address compare register 40 420h (rmw instruc- tions are pro- hibited.) romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? w? 0000000? target rom address (lower 7 bits) ? romcmp41 address compare register 41 421h (rmw instruc- tions are pro- hibited.) romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 w 00000000 target rom address (middle 8 bits) romcmp42 address compare register 22 422h (rmw instruc- tions are pro- hibited.) romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 w 00000000 target rom address (upper 8 bits) romsub4l address substitution register 4l 424h (rmw instruc- tions are pro- hibited.) roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 w 00000000 patch code (lower 8 bits) romsub4h address substitution register 4h 425h (rmw instruc- tions are pro- hibited.) roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 w 00000000 patch code (upper 8 bits) romcmp50 address compare register 50 428h (rmw instruc- tions are pro- hibited.) romc07 romc06 romc05 romc04 romc03 romc02 romc01 ? w? 0000000? target rom address (lower 7 bits) ? romcmp51 address compare register 51 429h (rmw instruc- tions are pro- hibited.) romc15 romc14 romc13 romc12 romc11 romc10 romc09 romc08 w 00000000 target rom address (middle 8 bits) romcmp52 address compare register 52 42ah (rmw instruc- tions are pro- hibited.) romc23 romc22 romc21 romc20 romc19 romc18 romc17 romc16 w 00000000 target rom address (upper 8 bits) romsub5l address substitution register 5l 42ch (rmw instruc- tions are pro- hibited.) roms07 roms06 roms05 roms04 roms03 roms02 roms01 roms00 w 00000000 patch code (lower 8 bits) romsub5h address substitution register 5h 42dh (rmw instruc- tions are pro- hibited.) roms15 roms14 roms13 roms12 roms11 roms10 roms09 roms08 w 00000000 patch code (upper 8 bits)
page 310 2007-10-15 tmp91fw60 17. i/o port equivalent-circuit diagrams ? how to read circuit diagrams the circuit diagrams in this chapte r are drawn using the same gate symb ols as for the 74hc xx series stan- dard cmos logic ics. the signal named stop has a unique function. this si gnal goes active-high if the cpu sets the halt bit when the haltm[1:0] field in the syscr2 register is programmed to 01 (e.g., stop mode) and the drive enable (drve) bit in the same register is cleared. if the drve bit is set, the stop signal remains inactive (at logic 0). ? the input protection circuit has a resistor in the range of several tens to several hundreds of ohms. 17.1 equivalent circuit diagrams 1. p0 (ad0 to ad7), p1 (ad8 to ad15, a8 to a15), p2 (a16 to a23, a0 to a7) 2. pz0 (rd ), pz1 (wr ) 3. p5 (an0 to an7), p6 (an8 to an15) v cc 1wvrwvfcvc p-ch +prwv1wvrwv +prwvfcvc 1wvrwvgpcdng stop +prwvgpcdng n-ch 1wvrwv v cc 1wvrwvfcvc stop p-ch n-ch #pcnqikprwv ejcppgnugngev #pcnqikprwv v cc 1wvrwvfcvc p-ch +prwv1wvrwv +prwvfcvc 1wvrwvgpcdng stop +prwvgpcdng n-ch
page 311 2007-10-15 tmp91fw60 4. pz2 (hwr ), pz3 (r/w ), p44(ale) 5. p40(cs0 /scout), p41(cs1 /txd2), p42(cs2 /rxd2), p43(cs3 /sclk2/cts2 ) 6. p75 (int0) 7. p32(wait /tb3out0), p33(tb3out1), p70(ta0in), p71(ta1out), p72(ta3out), p73(ta4in), p74(ta5out), p80 to p87,p91(rxd0), p92(sclk0/cts0 ), p94(rxd1), p95(sclk1/cts1 ), pa0 to pa3,pb2(tb4out0), pb3(tb4out1) +prwv1wvrwv +prwvgpcdng vcc 1wvrwvfcvc 1wvrwvgpcdng stop +prwvfcvc vcc 2tqitcoocdng rwnnwrtgukuvqt p-ch n-ch +prwv1wvrwv +p r wvgpcdng v cc 1wvrwvfcvc 1wvrwvgpcdng stop +prwvfcvc vcc 2tqitcoocdng rwnnwrtgukuvqt p-ch n-ch +prwv1wvrwv uejokvvvtkiigt v cc 1wvrwvfcvc 1wvrwvgpcdng stop +prwvfcvc  p-ch n-ch v cc 1wvrwvfcvc p-ch +prwv1wvrwv +prwvfcvc 1wvrwvgpcdng stop +p r wvgpcdng n - ch
page 312 2007-10-15 tmp91fw60 8. p30(tb3in0/int3/sda0), p31( tb3in1/int4/scl0), p90(txd0), p93(txd1), pb0(tb4in0/int9/ sda1), pb1(tb4in1/int10/scl1) 9. p96 (xt1), p97 (xt2) 10. nmi 11. am0 to am1 12. reset +prwv1wvrwv +p r wvgpcdng v cc 1wvrwvfcvc stop +prwvfcvc 1rgpftckp qwvrwvgpcdng  p-ch n-ch p96(xt1) p97(xt2) stop ^ vcc vcc +prwvfcvc 1wvrwvfcvc 1wvrwvgpcdng +prwvfcvc 1wvrwvfcvc 1wvrwvgpcdng .qyhtgswgpe[queknncvqtgpcdng +prwvgpcdng +prwvgpcdng %nqem 1ueknncvqtektewkv p-ch n-ch p-ch n-ch +prwv nmi 5ejokvvvtkiigt +prwv +prwv wdtout 4gugv 4gugvgpcdng 5ejokvvvtkiigt p-ch vcc
page 313 2007-10-15 tmp91fw60 13. x1, x2 14. vrefh, avss x2 *kijhtgswgpe[ queknncvqtgpcdng 1ueknncvqtektewkv p - ch n - ch %n qe m  x1 v refh vrefon a vss p-ch .cffgttgukuvqtu
page 314 2007-10-15 tmp91fw60 18. points to note and restrictions 18.1 notation a. the notation for built-in i/o registers is as follows register symbol e.g.) ta01run denotes bit ta0run of register ta01run. b. read-modify-write instructions an instruction in which the cpu reads data from memo ry and writes the data to the same memory loca- tion in one instruction. example 1: set 3, (ta01run) ... set bit3 of ta01run. example 2: inc 1, (100h) ... increment the data at 100h. ? examples of read-modify-write instructions on the tlcs-900 exchange instruction ex (mem), r arithmetic operations add (mem), r/# adc (mem), r/# sub (mem), r/# sbc (mem), r/# inc #3, (mem) dec #3, (mem) logic operations and (mem), r/# or (mem), r/# xor (mem), r/# bit manipulation operations stcf #3/a, (mem) res #3, (mem) set #3, (mem) chg #3, (mem) tset #3, (mem) rotate and shift operations rlc (mem) rrc (mem) rl (mem) rr (mem) sla (mem) sra (mem) sll (mem) srl (mem) rld (mem) rrd (mem) c. f osch , fc , fs , f fph , f sys and one state the clock frequency input on pins x1 and 2 is called f osch or fc. the clock selected by syscr1 is called f fph . the clock frequency give by f fph divided by 2 is called f sys . one cycle of f sys is referred to as one state.
page 315 2007-10-15 tmp91fw60 18.2 points of note a. am0 and am1 pins this pin is connected to th e dvcc pin. do not alter the level when the pin is active. b. emu0 and emu1 pins open pins. c. halt mode (idle1) when idle1 mode (in which oscillator operati on only occurs) is used, set rtccr to 0 stop the special timer for clock befo re the halt instructions is executed. d. warm-up counter the warm-up counter operates when stop mode is re leased, even if the syst em is using an external oscillator. as a result a time equivalent to the warm -up time elapses between input of the release request and output of the system clock. e. programmable pull-up/pull-down resistances the programmable pull-up/pull-down resistor can be turned on/off by a prog ram when the ports are set for use as input ports. when the ports are set for use as output ports , they cannot be turned on/off by a program. the data registers (e.g., p4) are used to turn the pull-up/pull-down resistors on/off. consequently read-modify-write instru ctions are prohibited. f. watchdog timer the watchdog timer starts operation immediately after a reset is released. when the watchdog timer is not to be used, disable it. when the bus is released, neither internal memory nor internal i/o can be acce ssed. however, the inter- nal i/o continues to operate. hen ce the watchdog timer continues to ru n. therefore be careful about the bus releasing time and set the detection timer of watchdog timer. g. cpu (micro dma) only the ldc cr, r and ldc r, cr instructions can be used to access the control registers in the cpu (e.g., the transfer source address register (dmasn)). h. undefined sfr the value of an undefined bit in an sfr is undefined when read. i. pop sr instruction please execute the pop sr instruction during di condition. j. clocks for serial channels (sio) as for the serial channels sio0, si o1 and sio2, a baud rate generator is unavailable as an input clock of an i/o interface and a clock for a serial tran sfer if a prescaler clock is set to fc/16 when syscr0 is "1".
page 316 2007-10-15 tmp91fw60 19. package dimension lqfp100-p-1414-0.50f unit: mm
page 317 2007-10-15 tmp91fw60 qfp100-p-1420-0.65a unit: mm
postscript this is a technical document that describes the oper ating functions and electrical specifications of the 16- bit microcontroller series tlcs-900/l1 (lsi). toshiba provides a variety of development tools an d basic software to enable efficient software development. these development tools have specifications that suppo rt advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and soft ware are supported continuou sly with version updates. the recent advances in cmos ls i production technology have been phenomenal and microcomputer systems for lsi design are constantly being improved. the products described in this document may also be revised in the future. be sure to check the latest specifications before using. toshiba is developing highly integrated, high-performance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variety of application areas. we are confident that our products can satisfy your application needs now and in the future.